Interposer Frame Layout for Overlay-Resistant Lithography
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Solution Overview
Problem
Overlay variations during lithographic exposure in semiconductor manufacturing lead to misalignment and defects in advanced package structures, such as chip-on-wafer-on-substrate (CoWoS) and integrated fan-out (InFO) packages, compromising device integrity and increasing defect rates.
Innovation Solution
A frame layout for lithographic exposure is designed to minimize unirradiated areas in distal redistribution dielectric layers by using negative photoresist materials without direct irradiation, employing anisotropic etching and ashing processes to form patterned photoresist layers, thereby reducing topographical defects and enhancing manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic exposure is used with standard frame layout, then manufacturing process is simple, but overlay variations cause misalignment and defects in distal redistribution dielectric layers
Solution Approach 1:
The frame layout is segmented into multiple irradiation zones with different exposure patterns. Central regions receive full irradiation while distal regions use reduced or no irradiation, allowing differential treatment of different wafer areas to compensate for overlay variations at different positions.
Solution Approach 2:
Different regions of the wafer are assigned different exposure qualities - central regions receive standard exposure while distal regions receive reduced or zero exposure. This local differentiation addresses the position-dependent overlay variations without requiring uniform changes across the entire wafer.
2Productivity
If sequential stepping exposure is used to cover large wafer areas, then productivity is improved, but cumulative alignment deviations increase
Solution Approach 1:
The frame layout is pre-configured with strategically positioned unirradiated areas and adjusted irradiation patterns before exposure begins. This preliminary design anticipates and compensates for cumulative alignment deviations that will occur during sequential stepping, eliminating the need for post-exposure correction.
3Manufacturing precision
If complete irradiation of distal redistribution dielectric layers is applied, then exposure uniformity is maintained, but undesirable trenches form due to overlay variations
Solution Approach 1:
The invention converts the potentially harmful effect of overlay variations into a beneficial outcome by strategically placing unirradiated areas in distal regions. These unirradiated zones prevent trench formation caused by misalignment while the overall exposure uniformity is maintained through the designed irradiation pattern.
4Manufacturing precision
If negative photoresist materials are used without direct irradiation in certain areas, then topographical defects are reduced, but process complexity increases
Solution Approach 1:
The irradiation pattern is made dynamic and adaptive rather than uniform. The exposure system adjusts irradiation delivery based on position-specific requirements, allowing negative photoresist materials to remain unirradiated in certain areas while receiving exposure in others, thereby reducing topographical defects without requiring fundamental process changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed frame layout minimizes undesirable trenches and improves the reliability and yield of organic interposer dies by ensuring precise alignment and uniform exposure, addressing overlay variations and enhancing the quality of semiconductor devices.
Implementation Method 1
employing anisotropic etching and ashing processes to form patterned photoresist layers
Implementation Method 2
a first photomask pattern is projected onto a first wafer to form a first lithographic exposure pattern
Data Source
AI summary
A reconstituted wafer is formed, which includes a two-dimensional array of interposer dies that are interconnected to one another and a two-dimensional array of semiconductor die sets. The two-dimensional array of interposer dies includes distal redistribution dielectric layers that are composed of dielectric negative photoresist materials and embed distal redistribution wiring interconnects. A lithographic exposure process sequentially lithographically exposes areas of the dielectric negative photoresist materials. Each illumination area includes an entirety of a laterally-sealed area enclosed by a respective edge seal ring structure, and further includes a respective adjacent kerf area such that a double-exposed area is formed between each neighboring pair of interposer dies.