Interposer Frame Vertical Interconnects for Semiconductor Packaging
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Solution Overview
Problem
Conventional fan-out wafer level chip scale package (Fo-WLCSP) processes for semiconductor devices are complex and costly due to the need for complicated conductive pillar and redistribution layer (RDL) formation for z-direction vertical electrical interconnects.
Innovation Solution
The method involves using an interposer frame with conductive pillars to provide vertical electrical interconnects by mounting the interposer over a semiconductor die, depositing an encapsulant, and forming an interconnect structure, thereby simplifying the assembly process and reducing the need for RDL patterning and conductive pillar formation through the encapsulant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conductive pillar and RDL formation processes are used for z-direction vertical electrical interconnects, then effective vertical electrical interconnect is achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
Conductive pillars are pre-formed on the interposer frame before mounting the semiconductor die. This preliminary formation of conductive structures eliminates the need for subsequent RDL patterning and conductive pillar formation through the encapsulant, significantly reducing manufacturing complexity while maintaining effective vertical electrical interconnects
Solution Approach 2:
An interposer frame with pre-formed conductive pillars serves as an intermediary component between the semiconductor die and the final package structure. This interposer provides the vertical interconnect function without requiring complex RDL formation processes, acting as a mediator that simplifies the overall manufacturing process
2Reliability
If conventional conductive pillar and RDL formation processes are used for z-direction vertical electrical interconnects, then effective vertical electrical interconnect is achieved, but manufacturing cost increases
Solution Approach 1:
Conductive pillars are pre-formed on the interposer frame before mounting the semiconductor die. This preliminary formation of conductive structures eliminates the need for subsequent RDL patterning and conductive pillar formation through the encapsulant, significantly reducing manufacturing complexity while maintaining effective vertical electrical interconnects
Solution Approach 2:
The interposer frame with pre-formed conductive pillars serves as a disposable intermediate component that enables vertical interconnect without requiring expensive RDL formation processes. The interposer is eventually removed or integrated, providing a cost-effective alternative to complex conventional manufacturing
3Reliability
If RDL patterning and conductive pillar formation are performed through encapsulant, then vertical electrical interconnect is achieved, but manufacturing time increases
Solution Approach 1:
Conductive pillars are pre-formed on the interposer frame before mounting the semiconductor die. This preliminary formation of conductive structures eliminates the need for subsequent RDL patterning and conductive pillar formation through the encapsulant, significantly reducing manufacturing complexity while maintaining effective vertical electrical interconnects
Data Source
AI summary
A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.


