Interposer Global ESD Bus for Cross-Chip Protection
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Solution Overview
Problem
Current ESD protection schemes for 2.5D/3D integrated circuit structures are limited to intra-chip protection and lack a robust cross-chip ESD discharge path, increasing the risk of ESD failure at chip-to-chip interfaces.
Innovation Solution
A global ESD bus is integrated into the interposer, connected to each chip's ESD bus, providing a continuous ESD protection network across the entire I/O domain for robust cross-chip ESD protection, utilizing a conductive mesh or ring layout within the interposer to facilitate efficient ESD current discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global ESD bus is integrated into the interposer, then cross-chip ESD protection is improved, but interposer complexity increases
Solution Approach 1:
The ESD bus in the interposer is designed to serve multiple functions: it provides ESD discharge paths for multiple chips simultaneously, acts as a ground reference plane, and maintains signal integrity for I/O connections. This multi-functionality reduces the need for separate dedicated ESD structures, thereby limiting the increase in complexity while achieving comprehensive cross-chip protection.
Solution Approach 2:
The ESD bus is integrated using the same conductive materials and fabrication processes as the existing interposer interconnect structure. By making the ESD bus homogeneous with the interposer's existing conductive layers, the patent avoids introducing fundamentally new structures or materials, thereby minimizing the increase in manufacturing complexity while providing robust cross-chip ESD protection.
2Reliability
If ESD discharge paths are minimized, then ESD protection performance is improved, but design flexibility deteriorates
Solution Approach 1:
The patent resolves the conflict between minimized discharge paths and design flexibility by transitioning from two-dimensional planar ESD paths to three-dimensional vertical paths through the interposer. The ESD bus extends vertically through multiple conductive layers of the interposer, providing short discharge paths in the vertical dimension while maintaining horizontal design flexibility for I/O routing and chip placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a global ESD bus in the interposer enhances ESD protection by providing a comprehensive cross-chip discharge path, reducing the risk of ESD failure and improving ESD performance by minimizing discharge paths and maintaining flexibility in interconnect designs.
Implementation Method 1
A global ESD bus is integrated into the interposer, connected to each chip's ESD bus, providing a continuous ESD protection network across the entire I/O domain for robust cross-chip ESD protection, utilizing a conductive mesh or ring layout within the interposer to facilitate efficient ESD current discharge
Data Source
AI summary
An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices.