Interposer Package Structure With Grooved Singulation Protection
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Solution Overview
Problem
The semiconductor industry faces challenges in the packaging process of Chip-on-Wafer-on-Substrate (CoWoS) package structures, particularly in preventing damage to the interconnect structure during pre-cut and sawing processes, which can lead to cracking or chipping issues.
Innovation Solution
The process involves forming intersected grooves on the interposer wafer through non-contact pre-cut processes like laser grooving and subsequent wafer dicing, followed by a wafer sawing process, where the grooves protect the interconnect structure from damage by maintaining a distance from the cutting blades, and an insulating encapsulation is used to encapsulate the semiconductor dies and underfills, ensuring reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact-based pre-cut and sawing processes are used, then manufacturing efficiency is maintained, but the interconnect structure is damaged causing cracking or chipping
Solution Approach 1:
Grooves are formed on the interposer wafer surface before the sawing process to create a protective barrier. This preliminary action positions the interconnect structure away from the saw blade path, preventing contact and potential damage during subsequent cutting operations.
Solution Approach 2:
The grooves act as an intermediary protective feature between the interconnect structure and the saw blade. By introducing this intermediate element, the direct harmful contact between the blade and delicate interconnect structures is avoided, allowing safe separation of the wafer.
2Area of stationary object
If the interconnect structure is kept close to the wafer edge for compact design, then device size is reduced, but the structure becomes vulnerable to damage during cutting
Solution Approach 1:
Instead of moving the interconnect structure further from the wafer edge in the lateral dimension, the solution introduces a vertical dimension feature (grooves) on the wafer surface. This allows the interconnect structure to remain in its compact lateral position while being protected by the groove barrier that extends into the wafer thickness direction.
Solution Approach 2:
The grooves are formed in advance to create a safe zone for the interconnect structure. This preliminary structuring ensures that even when the interconnect is positioned close to the edge for compactness, the pre-formed grooves will protect it during subsequent cutting operations.
3Manufacturing precision
If multiple cutting passes are performed to achieve precise singulation, then cutting precision is improved, but processing time and risk of damage increase
Solution Approach 1:
The grooves are formed as a preliminary feature that serves dual purposes: they act as cutting guides for precise blade positioning and simultaneously protect the interconnect structure. This eliminates the need for multiple conservative cutting passes, allowing single-pass accurate cutting without increased damage risk.
Solution Approach 2:
The grooves perform multiple functions simultaneously: they serve as alignment guides for the saw blade, create physical barriers to protect interconnect structures, and define the cut path. This multi-functionality consolidates what would otherwise require multiple separate operations into a single cutting pass.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents cracking or chipping of the interconnect structure during processing, enhances the reliability of electrical connections, and allows for the efficient fabrication of singulated package structures with improved yield and reduced costs.
Implementation Method 1
forming intersected grooves on the interposer wafer through non-contact pre-cut processes like laser grooving
Data Source
AI summary
A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.