Electrical Interposer Shielding for Fine-Pitch Crosstalk Isolation
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Solution Overview
Problem
Conventional electrical connectors face challenges in making separable connections for semiconductor devices with decreasing contact pitch, particularly below 500μm, and struggle with high-speed signal integrity due to noise and crosstalk issues, which are exacerbated by the need for additional PCB area and increased pin count.
Innovation Solution
The development of an electrical interposer with shielded contact probes and traces that include signal pins electrically coupled to ground pins and inner ground planes, providing effective shielding without increasing the connector size, thereby reducing noise and improving signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques are used to make separable electrical connections at 500-micron package pitch level, then connection reliability may be maintained, but manufacturing difficulty and cost increase prohibitively
Solution Approach 1:
The patent transitions from planar 2D connector layouts to a 3D stacked architecture where multiple connector layers are vertically arranged and electrically interconnected through through-substrate vias. This dimensional change allows high-density connections at 500-micron pitch while maintaining manufacturability by distributing connections across multiple layers rather than requiring all connections in a single plane.
Solution Approach 2:
The connector system is divided into multiple separable layers, each handling specific signal groups. The first connector layer handles certain differential pairs while the second layer handles others, with through-substrate vias providing vertical interconnection. This segmentation allows each layer to be optimized independently for its specific pitch and signal requirements, making manufacturing more manageable.
2Reliability
If grounded contact elements are positioned between every adjacent pair of differential signal pins to reduce crosstalk noise, then signal integrity improves, but pin count and connector size increase
Solution Approach 1:
The patent moves shielding from the horizontal plane to the vertical dimension by implementing ground planes on separate connector layers. Instead of placing ground contacts between every differential pair in the same layer (which would increase pin count), the design uses through-substrate vias to connect ground elements vertically, providing electrostatic shielding across layers without increasing the footprint or pin count of individual layers.
Solution Approach 2:
Through-substrate vias act as intermediaries to connect ground planes between layers, creating a vertical shielding structure. These vias provide the necessary electrical connection between ground elements on different layers, enabling effective crosstalk reduction without requiring additional ground contacts in the horizontal plane.
3Object-affected harmful factors
If conventional PCIe connectors are used with additional ground contacts for shielding, then crosstalk noise is reduced, but PCB area requirements increase
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple connector layers to achieve shielding functionality. Ground planes on adjacent layers provide electrostatic shielding for differential pairs without requiring additional horizontal space. The through-substrate vias enable this vertical stacking architecture, allowing high-density connections with effective shielding in a compact PCB footprint.
4Speed
If high signal frequencies are used to meet wide range application requirements, then data rate increases, but copper and power loss increase causing transmission distance to decrease
Solution Approach 1:
The stacked connector architecture with vertical interconnections through substrate reduces the horizontal trace lengths required for signals to travel between connection points. By utilizing the vertical dimension for signal routing and interconnection, the design minimizes copper loss while maintaining high data rates. The shorter effective transmission paths reduce both resistive losses and signal attenuation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables reliable, scalable, and compact electrical connections with improved signal integrity for semiconductor devices, even at high data rates, by effectively isolating differential signal pairs and reducing crosstalk, thus addressing the limitations of conventional connectors.
Implementation Method 1
Each pair of differential signal pins is electrically-shielded by at least one ground pin electrically-coupled to a ground plane
Data Source
AI summary
A separable and reconnectable connector for semiconductor devices is provided that is scalable for devices having very small contact pitch. Connectors of the present disclosure include signal pins shielded by pins electrically-coupled to ground. One or more signal pins in a contact array are electrically-shielded by at least one ground pin coupled to a ground plane. Embodiments thereby provide signal pins, either single-ended or a differential pair, usable to transmit signals with reduced noise or cross-talk and thus improved signal integrity. Embodiments further provide inner ground planes coupled to connector ground pins to shield pairs of differential signal pins without increasing the size of the connector. Inner grounding layers can be formed within isolation substrates incorporated into connector embodiments between adjacent pairs of signal pins. These buried ground layers provide additional crosstalk isolation in close proximity to signal pins, resulting in improved signal integrity in a significantly reduced space.