Interposer Structure for CMP-Free Hybrid Bonding Reliability
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Solution Overview
Problem
Current hybrid bonding techniques for devices and semiconductor wafers result in uneven bonding surfaces due to chemical mechanical polishing (CMP) processes, leading to decreased bonding strength and reliability.
Innovation Solution
An interposer structure with a conductive portion, dielectric layer, and wires is used to electrically connect substrates, where the dielectric layer encapsulates the conductive portion and exposes the surfaces for wire formation, eliminating the need for CMP processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) processes are performed on devices and semiconductor wafers before bonding, then the bonding surfaces can be flattened, but the CMP processes cause the bonding surfaces to become uneven, resulting in decreased bonding strength and device reliability
Solution Approach 1:
The patent applies preliminary action by forming a compensation layer on the bonding surface before the bonding process. This compensation layer is designed to compensate for surface irregularities that will occur during bonding, preventing the unevenness problem before it arises. The layer is formed in advance with specific material properties and thickness to offset anticipated surface variations, thereby maintaining bonding strength without requiring CMP processes.
Solution Approach 2:
The patent changes material parameters by introducing a compensation layer with specific mechanical and physical properties that differ from the substrate. This layer has controlled thickness, elasticity, and adhesion characteristics that allow it to absorb surface irregularities and provide a uniformly effective bonding interface, thus improving bonding reliability without compromising surface flatness through CMP.
2Manufacturing precision
If chemical mechanical polishing (CMP) processes are performed on devices and semiconductor wafers, then surface flatness can be improved, but the processes decrease bonding strength and increase manufacturing complexity
Solution Approach 1:
The patent extracts and eliminates the CMP process from the manufacturing sequence by replacing it with a compensation layer approach. Instead of using mechanical polishing to achieve surface flatness, the invention removes the CMP step entirely and uses a material layer to compensate for surface irregularities, thereby simplifying the manufacturing process while maintaining or improving bonding quality.
Solution Approach 2:
The patent changes the manufacturing approach by transitioning from a surface modification process (CMP) to a material addition process (forming compensation layer). This parameter change in the manufacturing methodology reduces process complexity by eliminating multiple CMP steps, associated equipment requirements, and process control parameters while achieving the same or better surface preparation results.
3Manufacturing precision
If chemical mechanical polishing (CMP) processes are performed on devices and semiconductor wafers, then surface flatness can be improved, but the processes increase manufacturing costs and decrease production yield
Solution Approach 1:
The patent extracts and removes the CMP process from the manufacturing flow, replacing it with a compensation layer formation process. This elimination of CMP steps reduces manufacturing costs by removing expensive equipment usage, consumable materials (slurries, pads), and process time, while simultaneously improving production yield by reducing the number of process steps where defects can occur.
Solution Approach 2:
The patent applies preliminary action by forming the compensation layer in advance during the same manufacturing cycle, which prevents surface irregularity problems before they affect bonding quality. This preliminary compensation approach improves yield by ensuring consistent bonding performance across all devices without requiring costly post-bonding repairs or rework.
Data Source
AI summary
An interposer structure and a package structure are provided. The interposer structure includes a conductive portion, a dielectric layer, a plurality of first wires, and a plurality of second wires. The conductive portion has a first surface and a second surface opposite to the first surface. The dielectric layer encapsulates the conductive portion and exposes the first surface and the second surface. The first wires are formed on the first surface. The second wires are disposed over the second surface.