Interposer-Based Imaging Sensor for High-Speed Inspection
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Solution Overview
Problem
Current semiconductor inspection systems are limited in speed, with existing image sensor technologies capable of processing only up to 10^9 pixels per second, making it impractical to scale beyond this level due to limitations in readout register design and capacitance issues.
Innovation Solution
The implementation of an interposer-based imaging device with integrated circuit elements such as charge conversion amplifiers, driver circuits, and digitizers on a silicon interposer, which includes a high thermal conductivity substrate for efficient heat dissipation and reduced capacitance, allowing for higher interconnect densities and increased processing speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple digitizers are mounted on the circuit board, then the capacitance between sensor outputs and digitizer inputs is reduced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the digitizers with the sensor array by fabricating both on the same silicon interposer substrate. This integration eliminates the need for separate mounting of digitizers on the circuit board, reducing assembly complexity while maintaining low capacitance between sensor outputs and digitizer inputs through close physical proximity.
Solution Approach 2:
The silicon interposer serves as an intermediary substrate that hosts both the sensor array and digitizers. This intermediate platform enables direct interconnection between sensors and digitizers with minimal parasitic capacitance, while the interposer itself can be mounted on a standard circuit board, simplifying the overall assembly process.
2Measurement precision
If the number of pixel elements is increased to improve resolution, then the measurement precision improves, but the readout speed and processing capability become insufficient
Solution Approach 1:
The patent segments the readout process by providing multiple independent readout registers, each capable of simultaneously reading out data from different portions of the sensor array. This parallel readout architecture enables high-resolution images to be captured and read out at high speeds, overcoming the bottleneck of sequential readout in conventional designs.
Solution Approach 2:
The patent adds a temporal dimension to the readout process by implementing time-division multiplexing across multiple readout registers. Different regions of the high-resolution sensor array are read out at different time intervals through multiple parallel channels, effectively increasing the overall readout speed without compromising spatial resolution.
3Measurement precision
If back-thinning is applied to maximize quantum efficiency, then the light sensitivity improves, but the mechanical strength and structural stability deteriorate
Solution Approach 1:
The patent employs a composite structure where the thinned sensor array is bonded to a robust silicon interposer substrate. The sensor array itself is back-thinned to maximize quantum efficiency, while the underlying silicon interposer provides the necessary mechanical strength and structural stability. This composite approach allows the sensor to achieve high light sensitivity without compromising structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster image processing and scaling capabilities beyond the limitations of prior art, enhancing the efficiency and speed of image sensor array inspection technologies.
Implementation Method 1
high thermal conductivity substrate for efficient heat dissipation
Data Source
AI summary
The present invention includes an interposer disposed on a surface of a substrate, a light sensing array sensor disposed on the interposer, the light sensing array sensor being back-thinned and configured for back illumination, the light sensing array sensor including columns of pixels, one or more amplification circuitry elements configured to amplify an output of the light sensing array sensor, the amplification circuits being operatively connected to the interposer, one or more analog-to-digital conversion circuitry elements configured to convert an output of the light sensing array sensor to a digital signal, the ADC circuitry elements being operatively connected to the interposer, one or more driver circuitry elements configured to drive a clock or control signal of the array sensor, the interposer configured to electrically couple at least two of the light sensing array sensor, the amplification circuits, the conversion circuits, the driver circuits, or one or more additional circuits.