Interposer Insulating Layer for Semiconductor Package Warpage Control
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Solution Overview
Problem
Current semiconductor packages face challenges in increasing storage capacity while maintaining a thin and lightweight design, and they struggle with structural reliability due to thermal expansion differences between semiconductor substrates and interposer substrates, leading to warpage and bonding defects during thermal compression bonding.
Innovation Solution
The implementation of an interposer structure with an interposer insulating layer between the semiconductor substrate and the interposer substrate, which includes a redistribution structure, conductive posts, and a molding layer, facilitates electrical connections and supports semiconductor chips, reducing warpage and the need for underfill layers, thereby enhancing structural reliability and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal compression bonding is performed to mount semiconductor chip on interposer structure, then electrical connection between chip and interposer is achieved, but warpage occurs due to difference of coefficients of thermal expansion between semiconductor substrate and interposer substrate
Solution Approach 1:
The patent introduces an interposer insulating layer as an intermediary component between the semiconductor substrate and interposer substrate. This interposer insulating layer acts as a mediator that reduces the impact of thermal expansion differences, preventing warpage while allowing thermal compression bonding to proceed effectively for electrical connection.
Solution Approach 2:
The patent employs composite material structure by combining the interposer insulating layer with the interposer substrate to form a composite assembly. This composite structure has optimized thermal expansion characteristics that match better with the semiconductor substrate, reducing warpage during thermal processing while maintaining electrical connection functionality.
2Reliability
If underfill layer process is performed to fill space between semiconductor chips and interposer structure, then structural support and stress relief are improved, but manufacturing time is increased
Solution Approach 1:
The patent extracts or removes the underfill layer process from the manufacturing sequence by designing the interposer insulating layer to provide sufficient structural support and stress relief functionality on its own, eliminating the need for the separate underfill layer application step and reducing manufacturing time.
Solution Approach 2:
The interposer insulating layer is designed to perform multiple functions: it provides electrical insulation, structural support, stress relief, and warpage prevention, replacing what would traditionally require separate underfill layer functionality. This multi-functionality eliminates the need for the dedicated underfill process.
Data Source
AI summary
An interposer structure includes: an interposer substrate; an interposer through electrode penetrating through the interposer substrate in a vertical direction; a redistribution structure on the interposer substrate and including a redistribution pattern connected to the interposer through electrode and a redistribution insulating layer on side surfaces of the redistribution pattern on the interposer substrate; a conductive post on the redistribution structure and connected to the redistribution pattern; and an interposer insulating layer on side surfaces of the conductive post on the redistribution structure.