Interposer Interconnections for 3D IC Packaging Height Reduction
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges in accommodating high-speed devices, particularly in terms of cooling, reliability, and cost-effectiveness, with increasing complexity and risk of errors during manufacture, while struggling to meet the demands of next-generation portable electronics that require smaller footprints, lower costs, and improved performance.
Innovation Solution
The method involves an integrated circuit packaging system that includes a routing structure with a functional side, a vertical interconnect extending from the routing structure, and an encapsulation that exposes the routing structure's surface and a portion of the interconnect, allowing for the mounting of external package components and their encapsulation, utilizing interposer interconnections to reduce complexity and enhance manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current packaging technologies are used for high-speed devices, then device functionality is achieved, but package height and manufacturing complexity increase
Solution Approach 1:
The patent transitions from traditional planar packaging to three-dimensional vertical packaging by implementing stacked interposer structures with through-silicon vias (TSVs). This allows signals and power to be routed vertically through multiple layers, enabling high-density integration while reducing the horizontal footprint and overall package complexity despite increased vertical dimension.
Solution Approach 2:
The patent employs nested interposer structures where smaller functional interposers are embedded within larger substrate interposers. This hierarchical nesting allows multiple functions to be integrated at different levels, reducing the need for separate discrete components and simplifying the overall package architecture while maintaining high-speed device functionality.
2Reliability
If advanced packaging structures are implemented, then device performance improves, but manufacturing time and cost increase
Solution Approach 1:
The patent performs preliminary routing and interconnection setup during the interposer fabrication stage before final device assembly. Through-silicon vias and conductive pathways are pre-formed in the interposer structures, allowing subsequent device mounting and wire bonding to proceed more quickly without requiring complex post-assembly routing operations.
Solution Approach 2:
The patent divides the packaging system into modular segments: substrate interposer, functional interposers, and device modules. Each segment can be fabricated, tested, and prepared independently using standardized processes, then assembled through automated pick-and-place operations. This segmentation enables parallel manufacturing of multiple components, reducing overall production time while maintaining high performance.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.