Interposer Interface Routing for Die Bus Crossing Reduction
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Solution Overview
Problem
The increasing physical limits of transistor size in semiconductor processes at 3 nm or 2 nm lead to higher costs and complexity due to line crossing issues when interfaces of dies are connected to a board, affecting chip logic and packaging.
Innovation Solution
An integrated apparatus using an interposer to connect switching and line logic blocks to different interfaces of a die, reducing area, cost, and power consumption by exchanging interfaces via the interposer, and employing a redistribution layer and active components for enhanced signal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dies are packaged together in manners such as rotation and symmetrization, then chip logic and packaging are simplified, but line crossing occurs when interfaces of the die are connected to a board
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the die and the board. The interposer includes a redistribution layer that routes signals from the die interfaces to the board connectors, eliminating the need for direct connections that would cause line crossing. This mediator allows the die to maintain its original orientation while still achieving proper signal routing to the board.
Solution Approach 2:
The patent moves the interface exchange function from the die level to the interposer level, effectively adding a dimensional layer to the connection architecture. By placing the redistribution layer on the interposer rather than within the die, the solution resolves line crossing issues without complicating the die design or requiring complex packaging arrangements.
2Object-generated harmful factors
If interfaces of a die are exchanged directly within the die, then bus crossing problems are resolved, but area, costs, and power consumption of the die increase
Solution Approach 1:
The interposer serves as a dedicated intermediary structure that handles interface exchange and redistribution. By offloading this function from the die, the die itself remains compact and simple, while the interposer provides the necessary routing capabilities without consuming die area, cost, or power resources.
Solution Approach 2:
The patent segments the chip system into distinct functional components: the die containing the core logic, the interposer containing the redistribution layer for interface exchange, and the board. This segmentation allows each component to be optimized independently, with the interposer specifically handling the interface exchange function that would otherwise bloat the die.
3Object-generated harmful factors
If interfaces of a die are exchanged directly within the die, then bus crossing problems are resolved, but process requirements and costs increase
Solution Approach 1:
The interposer acts as a separate manufacturable component that can be produced using standard PCB or substrate fabrication processes. This approach avoids the need for complex, expensive, and difficult-to-manufacture modified die structures, making the overall system easier and more cost-effective to produce while still resolving the bus crossing problem.
4Object-generated harmful factors
If interfaces of a die are exchanged directly within the die, then bus crossing problems are resolved, but power consumption increases
Solution Approach 1:
The interposer provides passive or low-power active routing capabilities for signal exchange. By performing interface exchange outside the die, the solution reduces the power burden on the die itself, as the interposer can handle signal routing with minimal power consumption compared to implementing complex switching and routing logic within the die.
Data Source
AI summary
An integrated apparatus includes an interposer and a die located on the interposer. The die includes a switching logic block, a line logic block, a first interface, and a second interface. The switching logic block is configured to control data exchange of the die. The line logic block is configured to control data receiving and sending of the die, the switching logic block is connected to the first interface via the interposer, and the line logic block is connected to the second interface via the interposer.