Interposer Device Stack With 3D ISC Dies for Power Integrity
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Solution Overview
Problem
Conventional integrated stack capacitor (ISC) chips have insufficient capacitance to effectively improve the power integrity (PI) of semiconductor packages with high-performance circuits, such as those requiring high bandwidth memories and faster digital signals.
Innovation Solution
The development of an interposer with a device stack structure that includes multiple integrated stack capacitor (ISC) structures, allowing for increased capacitance and improved power integrity by stacking multiple ISC dies within the same area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional integrated stack capacitor (ISC) chips are used, then the structure is simple and manufacturing is easy, but the capacitance is insufficient to improve power integrity of high-performance circuits
Solution Approach 1:
The patent transitions from planar capacitor arrangement to three-dimensional stacking, placing multiple ISC dies vertically on top of each other on the interposer. This vertical stacking enables significantly higher total capacitance within the same footprint area, resolving the contradiction between increasing capacitance and maintaining structural simplicity.
Solution Approach 2:
The patent embeds multiple ISC dies within the interposer structure through vertical stacking, where each capacitor die is nested within the same spatial envelope. This nesting approach allows high capacitance density without increasing the overall package footprint, addressing the contradiction between capacitance quantity and device complexity.
2Quantity of substance
If multiple integrated stack capacitor (ISC) dies are stacked to increase capacitance, then power integrity improves, but warpage due to thermal expansion differences increases
Solution Approach 1:
The patent uses molding material with thermal expansion characteristics matched to the interposer substrate, creating a homogeneous thermal expansion profile throughout the stacked structure. This reduces differential thermal stress and minimizes warpage, allowing multiple ISC dies to be stacked without compromising structural stability.
Solution Approach 2:
The patent employs a composite structure consisting of the interposer substrate, multiple ISC dies, and specially formulated molding material. The molding material acts as a composite component that compensates for thermal expansion differences between the silicon-based ISC dies and the organic substrate, reducing warpage while maintaining the high capacitance benefit of stacked configuration.
3Quantity of substance
If high-capacitance capacitors are implemented to improve power integrity, then power noise suppression improves, but the package size increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple ISC dies on top of each other on the interposer, rather than expanding horizontally. This three-dimensional arrangement achieves high total capacitance while maintaining a compact package footprint, resolving the contradiction between capacitance quantity and package area.
Data Source
AI summary
An interposer including a first redistribution structure; a device stack structure on the first redistribution structure, the device stack structure including a first device die and a second device die on the first device die, and each of the first device die and the second device die including one or more integrated stack capacitor structures; a plurality of first connection members on the first redistribution structure; a molding material on the first redistribution structure, the molding material covering the device stack structure and the plurality of first connection members; and a second redistribution structure on the molding material.