Interposer Substrate Layout for Void-Free Semiconductor Packaging
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Solution Overview
Problem
In semiconductor packages with package-on-package structures, differences in semiconductor chip thicknesses cause uneven flow of molding material, leading to void formation and reduced heat dissipation efficiency.
Innovation Solution
The semiconductor package design includes an interposer substrate with varying part surfaces to match the intervals between the substrate and semiconductor chips of different heights, ensuring balanced molding material flow and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional interposer substrate with a uniform lower part surface is used, then the structure is simple and easy to manufacture, but voids form in the molding layer due to uneven molding material flow caused by different chip thicknesses
Solution Approach 1:
The interposer substrate's lower part surface is divided into multiple regions with different heights, where each region corresponds to a specific semiconductor chip. The height of each lower part surface region is specifically designed to match the thickness of the corresponding chip, ensuring uniform molding material flow intervals across all chips while maintaining a relatively simple overall substrate structure.
Solution Approach 2:
The lower part surface of the interposer substrate is segmented into multiple discrete height regions rather than being uniform. Each segment corresponds to a specific chip location and provides the appropriate interval for molding material flow, preventing void formation without requiring complete structural redesign of the entire substrate.
2Temperature
If the interval between the interposer substrate and semiconductor chips is not uniformly controlled, then the manufacturing process is simpler, but heat dissipation efficiency is reduced due to uneven molding layer thickness
Solution Approach 1:
Different regions of the interposer substrate's lower part surface are assigned different heights tailored to the specific thickness requirements of each semiconductor chip. This localized customization ensures that the interval between the substrate and each chip is optimally controlled for both molding material flow and heat dissipation, without requiring complex overall interval control mechanisms.
Data Source
AI summary
A semiconductor package including a lower substrate, a first lower semiconductor chip disposed on the lower substrate and a second lower semiconductor chip disposed adjacent to the first lower semiconductor chip on the lower substrate, and an interposer substrate including a first lower part surface disposed above and spaced apart from the first lower semiconductor chip and the second lower semiconductor chip, wherein a height of an upper surface of the first lower semiconductor chip is higher than a height of an upper surface of the second lower semiconductor chip, and a height difference between the upper surface of the first lower semiconductor chip and the first lower part surface of the interposer substrate is greater than a height difference between the upper surface of the first lower semiconductor chip and the second lower part surface of the interposer substrate.