Interposer Lid and Stiffener Structure for Low-Warpage IC Packaging
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Solution Overview
Problem
Existing electronic device packaging techniques face challenges in accommodating different pitch sizes of inputs and outputs, maintaining planarity, and structural stability, particularly for large devices with small die interconnect pitches, leading to signal integrity issues and increased packaging costs.
Innovation Solution
The use of an interposer with fan-out interconnects, a lid, and a stiffening structure to establish electrical connections between integrated circuit dies and substrates, while managing heat dissipation and mechanical stability through materials like Ajinomoto Build-up Film (ABF) substrates, copper, nickel, and thermal interface materials, and incorporating a trapezoid-shaped cross-section for mechanical support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If traditional packaging techniques are used for large electronic devices, then the device can be packaged, but structural stability and planarity deteriorate due to warpage issues
Solution Approach 1:
The patent introduces a stiffening structure with specific geometric parameters (thickness, material properties) to change the mechanical parameters of the packaging system. This stiffening structure modifies the stiffness and thermal expansion characteristics of the interposer assembly, thereby reducing warpage and improving planarity while maintaining structural stability.
Solution Approach 2:
The patent employs composite material structures including the interposer with stiffening structure, lid, and various interface materials. These composite structures combine materials with different thermal and mechanical properties to create an assembly that resists warpage while accommodating thermal expansion differences between components.
2Adaptability or versatility
If different pitch sizes of I/Os are accommodated, then versatility is improved, but device complexity increases
Solution Approach 1:
The interposer serves as an intermediary component between the integrated circuit die and the substrate. It provides a transition layer with intermediate pitch dimensions that facilitates electrical connection between components with different pitch sizes. The stiffening structure on the interposer further simplifies the design by providing mechanical support that enables larger substrate sizes without compromising signal integrity.
Solution Approach 2:
The patent transitions from a two-dimensional planar interconnection approach to a three-dimensional stacked architecture. By stacking the interposer, die, and substrate vertically with the stiffening structure providing mechanical support, the design accommodates different pitch sizes through vertical integration rather than horizontal expansion, reducing overall packaging complexity.
3Area of stationary object
If the substrate size is increased for large electronic devices, then the device capacity is improved, but manufacturing precision deteriorates due to warpage
Solution Approach 1:
The stiffening structure modifies the mechanical parameters of the interposer assembly by increasing its flexural rigidity. This parameter change reduces the susceptibility to warpage during manufacturing and assembly processes, thereby maintaining alignment precision even when the substrate size is increased for large electronic devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves signal quality, reduces packaging costs, and enhances mechanical stability by addressing warpage issues, enabling efficient heat dissipation and effective electrical interconnects across varying pitch sizes.
Implementation Method 1
The lid includes copper, which is plated with a layer of nickel, and is configured to spread heat that is generated when powering the integrated circuit die
Implementation Method 2
a layer of thermal interface material (TIM) disposed between the first section and the fourth surface and establish contact therebetween, the TIM being configured to transfer heat between the integrated circuit die and the first section
Data Source
AI summary
An electronic device disposed in a package that includes: an interposer, fan-out interconnect (FOI), and a lid. The interposer having first size and first surface upon which die terminals (DTs) are disposed and are configured to electrically couple to integrated circuit die (IC), and second surface upon which substrate terminals (STs) are disposed and are configured to electrically couple to substrate. The IC has second size smaller than the first size, and the IC is mounted on the first surface in electrical contact with the DTs, the interposer is mounted on third surface, and the package substrate has third size, larger than the first size. The FOI establishes electrical interconnection between DTs and STs, the DTs have first pitch size and the STs have second pitch size, larger than first pitch size. The lid has first section, configured to abut fourth surface, and second section, mounted on the third surface.