2.5D Electronic Package Warpage Control via Interposer Metallization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Warpage issues in integrated circuits due to thick metal layers in power distribution networks cause non-parallel bonding surfaces, leading to unacceptable convex or concave shapes, which are exacerbated by increasing die size, affecting contact quality and reliability.
Innovation Solution
A 2.5D electronic package design where multiple integrated circuits are mounted side-by-side on an interposer with thin metallization layers, and the interposer is connected to a package substrate using micro and C4 bumps, eliminating the need for a thick uppermost metallization layer in the integrated circuit, and adding metallization layers to the interposer for power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a thick uppermost metallization layer is used in the integrated circuit for power distribution, then power distribution capability is improved, but warpage increases causing non-parallel bonding surfaces
Solution Approach 1:
The power distribution function is segmented between the integrated circuit and the interposer. The IC provides lower metallization layers while the interposer provides additional metallization layers, distributing the power distribution capability across multiple components rather than relying on a single thick layer in the IC.
Solution Approach 2:
The interposer acts as an intermediary component between the integrated circuit and the package substrate. It provides the additional metallization layers needed for power distribution without requiring the IC itself to have thick metallization layers, thus resolving the conflict between power distribution capability and warpage control.
2Area of moving object
If die size is increased, then device functionality is improved, but warpage increases causing unacceptable convex or concave shapes
Solution Approach 1:
The system is segmented into multiple components (IC, interposer, package substrate) that can be independently fabricated and optimized. This allows larger die sizes to be used without compromising overall package flatness, as the interposer can compensate for warpage issues in larger ICs.
Solution Approach 2:
The design changes the metallization layer configuration parameter - using multiple thinner layers on the interposer instead of a single thick layer on the IC. This parameter change allows larger die sizes to be used while maintaining acceptable warpage levels through the distributed metallization approach.
3Productivity
If multiple integrated circuits are stacked one-on-top-of-the-other, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from three-dimensional stacking (3D packaging) to a two-dimensional side-by-side arrangement on the interposer, with the interposer itself providing vertical metallization layers. This dimensional change simplifies manufacturing compared to true 3D stacking while still achieving high integration density.
Data Source
AI summary
A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.