Interposer Mold Layer Geometry to Prevent Wafer Warpage
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Solution Overview
Problem
The fabrication of semiconductor packages using silicon-based interposers often results in wafer warpage due to differences in thermal expansion coefficients, leading to misalignment between semiconductor chips and pads, which affects the reliability of the package.
Innovation Solution
A semiconductor package design featuring a circuit board with an interposer structure, where a mold layer with constant side wall slope and specific trench configurations separates first and second semiconductor chips, and a heat slug covers the chips to enhance stability and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a semiconductor chip is mounted on a silicon-based interposer and then molded, then the package structure is formed, but wafer warpage occurs due to CTE difference between thin silicon and thick silicon, leading to misalignment between chip and pad
Solution Approach 1:
The mold layer is formed before mounting the semiconductor chip on the interposer. This preliminary formation of the mold layer with its specific geometric configuration (constant side wall slope and angle ≤90° at the bottom) provides a stable structural foundation that prevents wafer warpage from occurring during subsequent processing steps, thereby maintaining alignment precision between the chip and pad.
Solution Approach 2:
The patent specifies precise geometric parameters for the mold layer: a constant side wall slope and an angle defined by the bottom side and side wall that is less than or equal to ninety degrees. These parameter specifications ensure the mold layer provides optimal structural support to counteract thermal expansion differences, preventing warpage while maintaining manufacturing precision.
2Reliability
If the semiconductor chip is mounted first and then molded, then the package is fabricated, but misalignment between semiconductor chip and pad occurs
Solution Approach 1:
The mold layer is formed in advance before chip mounting, creating a stable geometric structure that prevents warpage during subsequent steps. This preliminary action ensures that the interposer remains flat and maintains precise alignment between the chip and pad, thereby improving package reliability.
Solution Approach 2:
The mold layer is designed with specific geometric parameters (constant side wall slope, angle ≤90° at bottom) that provide optimal mechanical support. These parameter specifications ensure the structure maintains its shape under thermal stress, preventing misalignment and improving overall package reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the reliability of the semiconductor package by preventing warpage and ensuring precise alignment of chips, thereby enhancing the package's stability and performance.
Implementation Method 1
a slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and wherein an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees
Implementation Method 2
a heat slug on the circuit board, the heat slug covering the logic chip and the memory chip
Implementation Method 3
the interposer structure includes an interposer, an interlayer insulating layer on the interposer, redistribution layers in the interlayer insulating layer, and a through via connected to the redistribution layer, and the redistribution layers are electrically connected to the logic chip and the memory chip
Data Source
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AI summary
A semiconductor package includes a circuit board (100), an interposer structure (220) on the circuit board, a first semiconductor chip (310) and a second semiconductor chip (320) on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer (400) between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.