Multi-chip Package Interposer with On-Package Decoupling Capacitors
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Solution Overview
Problem
As integrated circuit technology scales down, the increased power consumption and parasitic capacitance in multi-chip packages lead to elevated power distribution network resonance noise, necessitating additional decoupling capacitance that occupies valuable die area.
Innovation Solution
The implementation of a multi-chip package with an interposer structure and on-package decoupling capacitor circuitry, utilizing through-silicon vias and redistribution layers to optimize power supply routing and decoupling paths, allowing for programmable series resistance configurations to minimize resonance noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If additional decoupling capacitance is added to compensate for elevated PDN resonance noise, then power distribution network noise is reduced, but die area occupied by decoupling capacitor circuitry increases
Solution Approach 1:
The patent introduces an interposer structure as an intermediary component between the package substrate and the integrated circuit die. The interposer contains decoupling capacitor circuitry with programmable series resistance that acts as a mediator to reduce PDN resonance noise. This allows the decoupling functionality to be implemented outside the die, preventing noise from reaching the die while minimizing the die area occupied by decoupling capacitor circuitry.
Solution Approach 2:
The patent employs programmable series resistance configurations in the decoupling capacitor circuitry. By adjusting the series resistance parameter, the system can optimize the decoupling effectiveness across different frequency ranges and operating conditions. This parameter tuning allows for reduced die area occupation while maintaining effective noise reduction performance.
2Power
If integrated circuit technology scales to smaller device dimensions, then device performance improves, but power consumption increases
Solution Approach 1:
The patent extracts the decoupling capacitor circuitry from the integrated circuit die and places it in the interposer structure. This separation allows the die to maintain high performance with smaller dimensions while the external decoupling circuitry handles power noise management. The extraction of this functionality prevents it from consuming valuable die area and allows the die to focus on high-performance computing functions.
3Use of energy by moving object
If multiple dies are placed within a single integrated circuit package to reduce power consumption, then overall power consumption decreases, but parasitic capacitance and inductance in the power distribution network increase
Solution Approach 1:
The interposer structure serves as a mediator between multiple dies and the package substrate, providing controlled impedance pathways for power distribution. The programmable series resistance in the decoupling capacitor circuitry further mediates the effects of parasitic capacitance and inductance by damping resonances and stabilizing power delivery across the multi-die package.
Solution Approach 2:
By implementing programmable series resistance in the decoupling capacitor circuitry, the system can dynamically adjust electrical parameters to compensate for parasitic effects. This parameter control allows multiple dies to be packaged together with reduced power consumption while maintaining stable power delivery despite the presence of parasitic capacitance and inductance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power supply resonance noise and minimizes the area occupied by decoupling capacitor circuitry, enhancing power distribution network performance and efficiency.
Implementation Method 1
Decoupling capacitors are used to help provide more stable power supply voltages by shunting high frequency noise on direct current (DC) power supply lines to ground
Implementation Method 2
Through-silicon vias (sometimes referred to as through-substrate vias) may be formed in the interposer substrate. The through-silicon vias may be electrically connected to corresponding flip-chip bumps through conductive paths formed in the redistribution layer
Implementation Method 3
the interposer may include multiple series-connected through-silicon vias (TSVs)... programmable series resistance configurations to minimize resonance noise
Data Source
AI summary
A multi-chip package that includes multiple integrated circuits is provided. An integrated circuit in the multi-chip package may be mounted on an interposer. The interposer may be mounted on a package substrate. The integrated circuit may have internal power supply terminals coupled to on-package decoupling (OPD) capacitor circuitry that are formed as part of the package substrate. The power supply terminals on the integrated circuit may be coupled to conductive routing paths and through-silicon vias (TSVs) in the interposer via microbumps. The through-silicon vias in the interposer may be coupled to the OPD capacitor circuitry via flip-chip bumps. The conductive routing paths and the TSVs in the interposer may be coupled to the internal integrated circuit power supply terminals in a way that minimizes power supply resonance noise.