Interposer Openings Filled With Conductive Layer for Semiconductor Packages
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Solution Overview
Problem
Existing semiconductor packaging methods, such as wire bonding and flip-chip bonding, face challenges with slow operating speed, electrical characteristic deterioration, and unstable connections due to wire short-circuiting and void creation during underfill processes, which affect the reliability and mechanical stability of semiconductor packages.
Innovation Solution
A semiconductor device design that incorporates an interposer with openings filled with a conductive layer, allowing connection members to be inserted for stable electrical connection between a semiconductor chip and a substrate, eliminating the need for an underfill process and reducing package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding method is used to connect semiconductor chip and substrate, then electrical connection is achieved, but operating speed becomes slow and electrical characteristics deteriorate
Solution Approach 1:
The patent replaces the mechanical wire bonding system with a direct bump connection system. Metal bumps are formed on the semiconductor chip and directly connected to the substrate, eliminating the need for wire bonding. This substitution of connection mechanism achieves both fast operating speed through direct electrical contact and reliable electrical connection through robust bump joints.
2Area of stationary object
If bump forming method is used with fine pitch electrode arrangement, then chip size packaging is achieved, but bumps may short-circuit and electrical connection becomes unstable
Solution Approach 1:
The patent applies local quality by forming protective structures at specific locations between adjacent bumps. The fine pitch electrode arrangement is maintained for chip size packaging, while localized protective features are introduced between bumps to prevent short-circuiting. This selective modification of specific areas maintains the benefits of fine pitch while eliminating the short-circuit risk.
3Length of stationary object
If height between substrate and semiconductor chip is decreased to prevent bump short-circuiting, then package height is reduced, but voids are created during underfill process
Solution Approach 1:
The patent implements beforehand cushioning by maintaining an appropriate height between substrate and semiconductor chip, and introducing protective structures in advance between bumps. This pre-configured protective arrangement prevents bump short-circuiting while maintaining sufficient space to avoid void formation during the underfill process. The height is optimized to provide both protection and proper underfill flow characteristics.
4Quantity of substance
If number of electrode pads is increased in limited space to achieve fine pitch, then packaging density is improved, but bumps may short-circuit with adjacent bumps
Solution Approach 1:
The patent applies local quality by maintaining the high density of electrode pads for improved packaging, while introducing localized protective structures between adjacent bumps. These protective features are positioned specifically in the regions where short-circuiting risk exists, allowing maximum electrode pad density without compromising electrical connection reliability.
Data Source
AI summary
A semiconductor package includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first connection members on the first surface; a second structural body placed over the first structural body, and formed with second connection members on a surface thereof which faces the first surface of the first structural body; and an interposer interposed between the first structural body and the second structural body, and having a body which is formed with openings into which the first connection members and the second connection members are inserted and a conductive layer which is formed to fill the openings.