Disposable Interposer Oxidation Profiles for Gate Leakage Control
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in achieving optimal transistor performance due to variations in the quality and profile of disposable interposers during oxidation processes, affecting gate control and leakage.
Innovation Solution
A method involving different wet oxidation processes with varying chemical compositions and temperatures is applied to disposable interposers, converting NH bonds to Si—O bonds, resulting in interposers with distinct profiles that enhance transistor performance by controlling gate control and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional oxidation processes are used on disposable interposers, then the oxidation conversion is simple, but the interposer profile quality and consistency deteriorate
Solution Approach 1:
The oxidation process is divided into multiple sequential stages (first oxidation, second oxidation, third oxidation) with progressively increasing oxidation strength. Each stage uses different oxidation conditions (temperature, time, chemical composition) to achieve gradual conversion of NH bonds to Si-O bonds, resulting in controlled profile formation and improved interposer quality without excessive complexity
Solution Approach 2:
The oxidation process parameters are systematically changed across different stages: oxidation temperature increases (e.g., from 800°C to 1000°C), oxidation time varies, and chemical composition evolves (from dry oxygen to wet oxidation with H2O, H2, and O2). These parameter changes enable progressive oxidation that achieves desired profile quality while managing process complexity
2Productivity
If minimum feature sizes are reduced for increased integration density, then more components can be integrated, but variations in interposer quality and profile worsen
Solution Approach 1:
The multi-stage oxidation process is performed as a preliminary action before subsequent processing steps. By completing the oxidation conversion and profile formation early in the manufacturing sequence, the interposer quality is established and stabilized before further processing, reducing variations that would affect final device performance at scaled dimensions
Solution Approach 2:
The oxidation process maintains continuous useful action through sequential stages without interruption. The first, second, and third oxidation steps follow one another in sequence, ensuring continuous conversion of NH bonds to Si-O bonds and continuous profile refinement, which maintains consistency even as feature sizes are reduced for higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves improved transistor performance by creating interposers with tailored profiles, ensuring consistent quality and reduced leakage through controlled oxidation processes, thereby optimizing gate control.
Implementation Method 1
performing a first oxidation process on the first plurality of disposable interposers
Data Source
AI summary
A method includes forming a multilayer stack over a semiconductor region, wherein the multilayer stack comprises a plurality of sacrificial layers and a plurality of semiconductor nanostructures located alternatingly. The method further includes removing the plurality of sacrificial layers, forming a plurality of disposable interposers between the plurality of semiconductor nanostructures, performing an oxidation process on the plurality of disposable interposers, laterally recessing the plurality of disposable interposers to form lateral recesses between the plurality of semiconductor nanostructures, forming inner spacers in the lateral recesses, removing the plurality of disposable interposers, and forming a replacement gate in spaces between the plurality of semiconductor nanostructures.