Disposable Interposer Oxidation for Oxide Recess Profile Control

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Solution Overview

Problem

As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in maintaining the quality and performance of gate-all-around transistors, particularly in controlling the oxide recess profile during the formation of disposable interposers.

Innovation Solution

A method involving different wet oxidation processes with varying conditions and chemicals is applied to disposable interposers in specific device regions, altering the profile of these interposers to enhance transistor performance by converting NH bonds to Si-O bonds, resulting in varying shapes and qualities of inner spacers and gate stacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wet oxidation process is applied to disposable interposers, then oxide recess profile is improved and gate control ability is enhanced, but process complexity increases due to multiple oxidation steps with varying conditions

Engineering Contradiction:
Improveoxide recess profileVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The oxidation process is divided into multiple sequential steps, each with specific conditions (temperature, time, chemical composition) tailored to achieve different aspects of oxide recess profile control. This segmentation allows precise control over the oxidation reaction to form the desired U-shaped profile with proper dimensions and quality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the disposable interposer receive different oxidation treatments through selective masking and varying oxidation conditions in different process steps. This enables local optimization of the oxide recess profile in specific device regions while maintaining control over the overall structure.

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple wet oxidation processes with varying conditions are used, then inner spacer and gate stack quality is enhanced, but manufacturing time and process steps increase

Engineering Contradiction:
Improveinner spacer and gate stack qualityVSAvoidmanufacturing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The multiple oxidation steps are designed to progressively build and refine the oxide recess profile before subsequent processing steps. Each oxidation step prepares the structure for the next, ensuring that the final profile meets quality requirements while maintaining an efficient process flow without unnecessary intermediate steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The oxidation process parameters (temperature, time, chemical composition, pressure) are systematically varied across different process steps to achieve the desired oxide recess profile and material quality. By optimizing these parameters, the process achieves high reliability outcomes while minimizing the total number of steps and overall processing time.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the gate control ability and reduces source/drain-to-gate leakage by tailoring the oxide recess profile, thereby enhancing the performance of gate-all-around transistors.

Implementation Method 1

performing a first oxidation process on the first plurality of disposable interposers

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS20250349594A1Controllable oxide recess profile through various wet oxidation processes
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250349594A1 patent drawing
  • US20250349594A1 patent drawing
  • US20250349594A1 patent drawing

AI summary

A method includes forming a multilayer stack over a semiconductor region, wherein the multilayer stack comprises a plurality of sacrificial layers and a plurality of semiconductor nanostructures located alternatingly. The method further includes removing the plurality of sacrificial layers, forming a plurality of disposable interposers between the plurality of semiconductor nanostructures, performing an oxidation process on the plurality of disposable interposers, laterally recessing the plurality of disposable interposers to form lateral recesses between the plurality of semiconductor nanostructures, forming inner spacers in the lateral recesses, removing the plurality of disposable interposers, and forming a replacement gate in spaces between the plurality of semiconductor nanostructures.