Interposer Semiconductor Package for Dense 3D Chip Stacking
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high reliability due to limitations in integration density, thermal management, and mechanical stability, particularly as demand increases for high capacitance, thinning, and miniaturization of electronic products.
Innovation Solution
The semiconductor package design incorporates an interposer substrate with a substrate, lower and upper protective layers, through-vias, pads, interlayer insulating layers, and interconnection structures. This design allows for the stacking of semiconductor chips with specific thickness and width configurations, along with an encapsulant and connection conductors, to enhance reliability and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked vertically to increase integration density, then the number of components per package is improved, but thermal management and mechanical stability deteriorate
Solution Approach 1:
The patent transitions from planar 2D chip arrangement to 3D vertical stacking configuration. Multiple semiconductor chips are stacked in the thickness direction of the interposer substrate, utilizing the third dimension to increase integration density. The lowermost chip is bonded to the upper surface of the interposer substrate, with additional chips stacked above it, creating a vertical architecture that maximizes component density within the package volume.
Solution Approach 2:
The interposer substrate serves as an intermediary structure between the stacked semiconductor chips and the external circuit board. It provides mechanical support, electrical interconnection through through-vias, and thermal conduction pathways. The interposer substrate with thickness of 50-150 μm acts as a mediator that distributes mechanical stress and conducts heat away from the stacked chips, addressing both mechanical stability and thermal management challenges.
2Quantity of substance
If semiconductor chips are stacked vertically to increase integration density, then the number of components per package is improved, but mechanical stability deteriorates
Solution Approach 1:
The patent employs a composite structure consisting of the interposer substrate, multiple semiconductor chips, encapsulant, and protective layers. Each layer contributes different mechanical properties: the interposer substrate provides flexibility and stress distribution, the encapsulant provides structural support and protection, and the protective layers provide surface stability. This composite architecture enhances overall mechanical stability while maintaining vertical stacking for high integration density.
Solution Approach 2:
The encapsulant and protective layers are applied in advance to cushion and protect the stacked semiconductor chips from mechanical stress and environmental damage. The encapsulant completely surrounds the stacked chips, providing mechanical support and stress distribution before external forces are applied. This pre-cushioning approach prevents mechanical failure during assembly and operation.
3Reliability
If the lowermost semiconductor chip has greater thickness than upper chips, then electrical connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different thickness specifications to different positions in the stack: the lowermost chip has a thickness of 70-100 μm while upper chips have a thickness of 50-70 μm. This local quality differentiation ensures that the lowermost chip, which bears the primary mechanical load and provides the main electrical connection interface with the interposer substrate, has sufficient thickness for reliability. The upper chips can be thinner to reduce overall package height while maintaining electrical performance.
Solution Approach 2:
The patent specifies precise thickness parameters for different chip positions: lowermost chip thickness of 70-100 μm and upper chip thickness of 50-70 μm. These parameter changes are implemented during the chip selection and stacking process, allowing manufacturers to optimize the balance between connection reliability and package dimensions. The through-via dimensions and protective layer thickness are also carefully controlled to match the chip thickness variations.
Data Source
AI summary
A semiconductor package may comprise an interposer substrate including a substrate and a lower protective layer, a through-via passing through the substrate and the lower protective layer, a lower pad on the lower protective layer and in contact with the through-via, an interlayer insulating layer on an upper surface of the substrate, and an interconnection structure in the interlayer insulating layer, a plurality of first semiconductor chips on an upper surface of the interposer substrate and electrically connected to the interconnection structure, a second semiconductor chip on the upper surface of the interposer substrate apart from the plurality of first semiconductor chips and electrically connected to the interconnection structure, an encapsulant covering at least a portion of the plurality of first semiconductor chips and the second semiconductor chip and connection conductors on the lower surface of the lower protective layer and electrically connected to the lower pad.