Interposer-Defined Package Cavities for Dense Multi-Die Interconnects
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Solution Overview
Problem
Integrated circuit packages face challenges in achieving increased interconnect density and reduced cost while maintaining compact size, as higher component integration leads to increased package cost and yield loss due to build-up area and layer count.
Innovation Solution
The use of inter-fitted patches with protrusions to create cavities for embedded devices, allowing for X-Y and Z-disaggregation, reducing build-up area usage and isolating yield loss to smaller layer count patches, and supporting embedded multi-die interconnect bridges and photonics devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher component integration is used to increase interconnect density, then communication efficiency between integrated circuit devices is improved, but package cost increases due to increased build-up area and layer count
Solution Approach 1:
The substrate is divided into multiple regions with different interconnect densities. High-density interconnect regions are provided only where needed between integrated circuit devices, while low-density regions are provided in other areas. This segmentation reduces the overall build-up area and layer count required, thereby reducing package cost while maintaining high communication efficiency where required.
Solution Approach 2:
Different interconnect densities are provided in different regions of the substrate according to local requirements. The substrate includes high-density interconnect regions positioned between integrated circuit devices to enable efficient communication, and low-density regions in areas where high interconnect density is not needed, optimizing resource allocation and reducing overall package complexity.
2Quantity of substance
If higher component integration is used to increase interconnect density, then bandwidth capability is improved, but yield loss increases due to increased build-up area and layer count
Solution Approach 1:
The substrate is segmented into high-density and low-density interconnect regions. This segmentation allows the package to achieve high bandwidth capability in critical areas through high-density interconnects while reducing overall package complexity and layer count in non-critical areas, thereby reducing yield loss and improving reliability.
Solution Approach 2:
High interconnect density is provided locally between integrated circuit devices where high bandwidth capability is required, while lower interconnect density is provided in other regions. This local optimization ensures that bandwidth requirements are met without unnecessarily increasing the build-up area and layer count across the entire substrate, reducing yield loss.
3Ease of manufacture
If conventional substrate interconnection is used, then manufacturing is simpler, but package size increases due to reduced interconnect density
Solution Approach 1:
The substrate is segmented into regions with different interconnect densities. High-density interconnect regions are implemented using advanced techniques only where needed between integrated circuit devices, while other regions use conventional interconnection methods. This segmentation enables compact package size through high-density interconnects where required, while maintaining manufacturing simplicity through conventional methods in other areas.
Data Source
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AI summary
An electronic substrate may be fabricated having a primary interposer comprising a laminate with a metal via through the laminate, two or more secondary interposers attached to a first side of the primary interposer, where respective sidewalls of the two or more secondary interposers define one or more recesses over the primary interposer, and an embedded component within a recess of the one or more recesses defined by the respective sidewalls of the two or more secondary interposers. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.