Interposer Package Redistribution for High-Density Chip Bonding

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Solution Overview

Problem

Existing integrated circuit technologies face limitations in bonding chips directly onto substrates due to increased density and area constraints, necessitating improved methods for three-dimensional packaging that enhance integration density and electrical connectivity.

Innovation Solution

The use of a redistribution structure and multiple carriers to form package structures, allowing for smaller features and reduced processing costs, with electrical interconnections between integrated circuit devices, including logic and memory dies, through interconnect and redistribution layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If integrated circuit density is increased through repeated reductions in minimum feature size, then integration density improves, but the ability to bond the chip directly onto a substrate deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidbonding capability
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by introducing interposers that enable multiple chips to be stacked vertically. This dimensional change allows continued increase in integration density without further reduction in minimum feature size, thereby maintaining bonding capability while achieving higher density through vertical rather than horizontal scaling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces interposers as intermediary structures between the integrated circuit chip and the substrate. These interposers redistribute ball contact areas from the chip to a larger area, enabling reliable bonding while accommodating high-density interconnect requirements. The interposer acts as a mediator that decouples the bonding interface from the chip's fine-pitch requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If interposers are used to redistribute ball contact areas to a larger area, then bonding capability improves, but device complexity increases

Engineering Contradiction:
Improvebonding capabilityVSAvoidpackage structure
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent designs interposers to perform multiple functions simultaneously: they serve as bonding substrates, provide signal redistribution, enable three-dimensional stacking, and facilitate thermal management. By consolidating these functions into a single component rather than using separate elements for each function, the overall package complexity is reduced despite the added capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functions of multiple separate components (bonding substrate, interconnect layer, redistribution layer) into an integrated interposer structure. This consolidation simplifies the manufacturing process by reducing the number of assembly steps and components, thereby offsetting the increased structural complexity with process simplification.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If three-dimensional packaging with multiple chips is implemented, then integration density improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improveintegration densityVSAvoidalignment accuracy
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent incorporates alignment features and registration marks during the interposer fabrication process before chip mounting. These preliminary structures enable precise alignment of multiple chips during subsequent bonding operations, thereby reducing the actual alignment precision requirements during assembly while maintaining high overall manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12400878B2Integrated circuit package and method
Publication Date: 2025.08.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12400878B2 patent drawing
  • US12400878B2 patent drawing
  • US12400878B2 patent drawing

AI summary

A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.