Interposer Package Layout for Dense Chip Interconnects

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Solution Overview

Problem

Existing technologies have not effectively addressed the need for miniaturizing and lightweight semiconductor packages that require high density interconnects and high density interconnects, and the need for increasing the reliability of semiconductor chips in portable electronic devices.

Innovation Solution

The semiconductor package includes a redistribution layer and enhances the reliability of an interconnection between a plurality of semiconductor chips, using a base package substrate with a redistribution region, vertical conductive vias, and an interposer to improve the interconnection between semiconductor chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If wafer level packages are applied to efficiently arrange semiconductor chips in a limited structure, then the total thickness of semiconductor packages is reduced for miniaturization, but the need for increasing the capacity of memories continuously increases requiring high density interconnects

Engineering Contradiction:

Improvetotal thickness of semiconductor packageVSAvoidmemory capacity and interconnect density

Core Design Contradiction:

Volume of moving objectVSQuantity of substance

Solution Approach 1:

The patent introduces an interposer layer that adds a vertical dimension to the interconnection architecture. Through-electrodes penetrate the interposer substrate to establish vertical interconnects, transforming the traditional planar interconnection into a three-dimensional structure. This enables high-density interconnects and increased memory capacity while maintaining reduced package thickness by utilizing the vertical dimension for signal routing.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interposer acts as an intermediary component between the package substrate and semiconductor chips. It provides through-electrodes that serve as intermediate connection points, enabling efficient signal and power transmission between multiple chips and the package substrate. This intermediary structure facilitates high-density interconnects without increasing the overall package footprint or thickness.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If the capacity of memories is increased with high density interconnects, then memory capacity increases, but the complexity of interconnection structure increases

Engineering Contradiction:

Improvememory capacityVSAvoidinterconnection structure complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The interconnection structure is segmented into distinct functional layers: the package substrate, the interposer with through-electrodes, and the semiconductor chips. This segmentation allows each component to be optimized independently - the interposer handles high-density vertical interconnects through its through-electrodes, while the package substrate provides the base interconnection framework. This modular segmentation reduces overall system complexity despite increased memory capacity.

Inventive Principle:

Principle #1Segmentation

3Reliability

If redistribution layers are added to enhance interconnection reliability, then interconnection reliability improves, but manufacturing complexity increases

Engineering Contradiction:

Improveinterconnection reliabilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the redistribution layer function with the interposer structure. The interposer integrates through-electrodes, redistribution patterns, and substrate functions into a single component. This consolidation achieves enhanced interconnection reliability through improved signal routing and impedance control, while reducing manufacturing complexity by eliminating the need for separate redistribution layer fabrication processes that would be required in traditional multi-layer approaches.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12424561B2Semiconductor package including interposer

Publication Date: 2025.09.23 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.