Interposer Semiconductor Package With Embedded Capacitors for Fast Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in accommodating highly integrated semiconductor chips due to limitations of printed circuit boards, necessitating the development of interposer-based solutions that enhance electrical characteristics and economic feasibility.
Innovation Solution
A semiconductor package design incorporating a first interposer with a lower redistribution structure, upper redistribution structure, conductive posts, passive elements, and internal semiconductor chips, utilizing ceramic capacitors and silicon capacitors to improve signal transmission and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If printed circuit boards are used to accommodate highly integrated semiconductor chips, then PCB manufacturing is simple and cost-effective, but the PCB cannot accommodate high integration levels
Solution Approach 1:
An interposer is introduced as an intermediary component between the PCB and highly integrated semiconductor chips. The interposer includes redistribution structures with conductive posts, insulating layers, and connection terminals that enable high-density interconnections while maintaining PCB compatibility. This mediator allows the system to achieve high integration capability without requiring the PCB itself to be redesigned for high-density mounting.
2Reliability
If interposer-based solutions are developed to enhance electrical characteristics, then signal transmission improves, but manufacturing complexity increases
Solution Approach 1:
The interposer structure is segmented into distinct functional layers including lower redistribution structures, upper redistribution structures, and intermediate connection layers. Each layer is independently formed with specific functions: lower redistribution for PCB interface, upper redistribution for chip interface, and intermediate layers for vertical interconnections. This segmentation allows each layer to be optimized and manufactured separately, then assembled together, reducing overall manufacturing complexity despite the advanced electrical characteristics achieved.
3Speed
If signal transmission paths are reduced to improve signal response, then electrical characteristics improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar signal transmission to three-dimensional vertical transmission by stacking multiple redistribution structures and connection terminals in vertical layers. Signal paths are shortened by routing signals vertically through the interposer thickness rather than horizontally across the PCB surface. This dimensional change achieves fast signal response while the vertical stacking approach is more tolerant to alignment errors compared to high-density planar routing.
Data Source
AI summary
A semiconductor package may include a first upper semiconductor chip on a top surface of a first interposer. The first interposer may include a lower redistribution structure, an upper redistribution structure, conductive posts between the lower redistribution structure and the upper redistribution structure, a first passive element, and a first internal semiconductor chip. The lower redistribution structure may include a lower redistribution pattern and a lower insulating layer. The upper redistribution structure may include an upper redistribution pattern and an upper insulating layer above the lower redistribution structure. The first passive element and the first internal semiconductor chip may be between the upper redistribution structure and the lower redistribution structure and laterally apart from the conductive posts. The first passive element may be a ceramic capacitor.