Interposer Package Structure for Fine-Pitch Self-Aligned Joints
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable packages with high integration density due to the increasing difficulty of fabrication processes as feature sizes decrease, which affects the packaging of electronic components.
Innovation Solution
A method for forming a package structure that involves using a carrier substrate and interposer substrate with insulating and conductive layers, bonding chip structures and electronic devices through conductive bumps, and forming conductive pillars over conductive via structures without forming conductive pads, enabling self-aligned and fine-pitch joints for high I/O throughput and improved design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging methods are used with decreasing feature sizes, then integration density is improved, but fabrication difficulty increases
Solution Approach 1:
The packaging process is segmented into distinct stages: forming conductive via structures in the interposer substrate, bonding chip structures to conductive pads, and forming conductive bumps only where needed. This segmentation allows each step to be optimized independently, reducing overall fabrication difficulty while maintaining high integration density
Solution Approach 2:
Conductive via structures are formed in the interposer substrate before chip structures are bonded. This preliminary action establishes the conductive pathways in advance, allowing subsequent bonding and bump formation to proceed more easily without the complexity of aligning all conductive elements simultaneously
2Ease of operation
If conductive pads are formed before bonding, then alignment is simplified, but manufacturing complexity increases
Solution Approach 1:
The conductive pad formation step is extracted from the conventional sequence and replaced by forming conductive via structures in the interposer substrate before bonding. This removes the complexity of forming pads on the chip itself, while the via structures provide sufficient alignment reference through their positioning in the interposer
Solution Approach 2:
Instead of forming conductive pads on the chip and bonding to them, the approach inverts the sequence by forming conductive via structures in the interposer first, then bonding chip pads to exposed conductive structures. This inversion simplifies the bonding step while achieving the same alignment function
3Strength
If conductive bumps are made larger for reliability, then joint strength is improved, but pitch flexibility is reduced
Solution Approach 1:
Conductive bumps are formed only in specific locations where conductive via structures protrude from the interposer substrate, rather than uniformly across the entire chip. This localized approach allows bump size to be optimized for strength while the spacing is determined by the via structure positions, providing pitch flexibility
Solution Approach 2:
The conductive via structures in the interposer substrate have varying dimensions and spacing, allowing the conductive bumps formed on them to achieve different sizes and pitches. This parameter variation enables optimization of joint strength for each location while maintaining overall pitch flexibility for fine-pitch joints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size and cost of conductive bumps, allows for fine-pitch joints, and enhances the reliability and yield of the packaging process, improving the integration density and performance of semiconductor devices.
Implementation Method 1
bonding chip structures and electronic devices through conductive bumps
Data Source
AI summary
A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conducive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.