Interposer Semiconductor Package for Fine-Pitch Wiring Yield
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Solution Overview
Problem
The semiconductor packaging field faces challenges in forming wirings for fine bump pitches on large-area package substrates, which are necessary for high-performance semiconductor chips, while maintaining low manufacturing costs and high yield.
Innovation Solution
A semiconductor package design that includes a base substrate with a wiring pattern, an interposer substrate with redistribution patterns, a semiconductor structure, a heat dissipation structure, and connection bumps, where the redistribution patterns on the interposer substrate are designed with specific line and space standards to support high-performance semiconductor chips and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fine bump pitch wiring is implemented on large-area package substrates, then semiconductor chip performance is improved, but manufacturing cost increases and yield decreases
Solution Approach 1:
The patent divides the wiring structure into multiple segments: external connection bumps on the base substrate, lower connection bumps on the interposer substrate, and upper connection bumps connecting to the semiconductor chip. This segmentation allows each layer to be optimized independently, enabling fine pitch wiring (50-150 μm) to be achieved through progressive redistribution rather than requiring the entire large-area substrate to support the fine pitch directly, thus reducing manufacturing complexity and cost.
Solution Approach 2:
The patent transitions from two-dimensional wiring layout to three-dimensional redistribution across multiple layers. The interposer substrate introduces vertical stacking of connection bumps and redistribution patterns, allowing fine pitch wiring to be achieved by distributing connections across multiple vertical layers rather than compressing all connections into a single plane, thereby reducing the manufacturing difficulty and cost associated with ultra-fine 2D pitch.
2Manufacturing precision
If fine bump pitch wiring is implemented on large-area package substrates, then semiconductor chip performance is improved, but manufacturing yield decreases
Solution Approach 1:
By segmenting the connection structure into external, lower, and upper connection bumps across separate substrates (base substrate and interposer substrate), the patent reduces the risk of defects propagating through the entire wiring system. Each segment can be independently manufactured and tested, isolating potential failure points and improving overall manufacturing yield while still achieving fine pitch wiring performance.
Solution Approach 2:
The interposer substrate acts as a buffer or cushioning layer between the large-area base substrate and the fine-pitch semiconductor chip. This intermediate layer absorbs and distributes mechanical and thermal stresses, preventing stress concentration that could cause wiring failures during manufacturing processes, thereby protecting the fine pitch wiring and improving manufacturing yield.
3Manufacturing precision
If redistribution patterns with small line width and space are used, then fine pitch wiring is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent uses vertical stacking of redistribution patterns on the interposer substrate to achieve fine pitch wiring without requiring ultra-fine 2D line widths and spaces. By distributing connections across multiple vertical layers (lower and upper redistribution patterns), the horizontal pitch requirements are relaxed, reducing manufacturing complexity while still achieving the desired fine pitch performance at the chip interface.
Solution Approach 2:
The interposer substrate serves as an intermediary that translates between the coarse pitch of the large-area base substrate and the fine pitch required by the semiconductor chip. The redistribution patterns on the interposer substrate act as a mediation layer, progressively transforming the wiring pitch from coarse to fine across multiple connection layers, thereby reducing the complexity of directly implementing fine pitch on the entire large-area substrate.
Data Source
AI summary
A semiconductor package includes a base substrate including a wiring pattern, an interposer substrate including lower and upper redistribution patterns, a semiconductor structure, a heat dissipation structure, a plurality of external connection bumps disposed on a lower surface of the base substrate, a plurality of lower connection bumps disposed between the base substrate and the interposer substrate, and a plurality of upper connection bumps disposed between the interposer substrate and the semiconductor structure.