Interposer Package Layout With IPD Integration for Signal Integrity
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Solution Overview
Problem
The increasing complexity of integrated circuit packages requires efficient methods to integrate multiple device dies, memory components, and Independent Passive Devices (IPDs) into a single package while ensuring high-density interconnections and minimizing signal integrity issues.
Innovation Solution
The integration of System-on-Chip (SoC) packages, memory components, and IPDs onto an interposer with low-RC interconnects and fine-line bridge dies, which are bonded using solder regions and redistribution lines to reduce Effective Series Resistance (ESR) and Effective Series Inductance (ESL), enhancing signal integrity and interconnection density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple device dies, packages, and IPDs are incorporated in the same package to achieve more functions, then the functionality and integration density are improved, but the device complexity and interconnection difficulty increase
Solution Approach 1:
The package is segmented into multiple functional layers including first and second package components, each containing different device dies (SoC, memory, IPDs). This segmentation allows independent optimization of each layer while achieving high overall integration density and functionality.
Solution Approach 2:
The patent transitions from planar 2D packaging to 3D stacked packaging architecture, where device dies are vertically stacked across multiple package components separated by an interposer. This dimensional change enables significantly higher integration density without increasing footprint area.
2Productivity
If high-density interconnections are implemented to integrate more components, then the integration density is improved, but the signal integrity issues and ESR/ESL increase
Solution Approach 1:
An interposer is introduced as an intermediary component between the first and second package components. The interposer contains a second plurality of through-vias that provide low-RC interconnects, acting as a mediator to maintain signal integrity while enabling high-density vertical interconnections between stacked package layers.
Solution Approach 2:
The patent optimizes interconnection parameters by using through-vias with reduced resistance and capacitance (low-RC interconnects). This parameter change allows high-density interconnections to be formed while maintaining acceptable signal integrity and reducing ESR/ESL effects.
3Productivity
If through-vias are formed to connect package components, then the interconnection density is improved, but the manufacturing complexity and precision requirements increase
Solution Approach 1:
Through-vias are formed in the package components and interposer during preliminary manufacturing steps before final assembly. This preliminary action allows precise via formation and alignment to be established early in the manufacturing process, facilitating subsequent bonding operations.
Solution Approach 2:
The interposer with its plurality of through-vias is nested between the first and second package components, creating a hierarchical structure where the interposer's via structure is integrated within the overall package stack. This nesting approach simplifies the overall manufacturing by modularizing the via formation process.
Data Source
AI summary
A method includes bonding a first package component and a second package component to an interposer. The first package component includes a core device die, and the second package component includes a memory die. An Independent Passive Device (IPD) die is bonded directly to the interposer. The IPD die is electrically connected to the first package component through a first conductive path in the interposer. A package substrate is bonded to the interposer die. The package substrate is on an opposing side of the interposer than the first package component and the second package component.