Interposer Semiconductor Package for Compact Low-Noise Multi-Chip Layout
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved electrical characteristics and compact size while maintaining manufacturing cost-effectiveness, particularly in integrating multiple semiconductor chips and capacitors within a compact structure.
Innovation Solution
The semiconductor package design incorporates an interposer substrate with a first and second redistribution substrate, an interposer molding layer, and a connection semiconductor chip, along with a capacitor chip, to enhance electrical connectivity and reduce size, using conductive patterns and interposer bumps for efficient signal transmission and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips and capacitors are integrated within a compact structure, then the device size is reduced, but the electrical characteristics and signal integrity deteriorate
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the package substrate and semiconductor chips. The interposer substrate includes first and second redistribution substrates with conductive patterns that route signals, and an interposer molding layer that provides physical support and electrical isolation. This mediator enables compact integration while maintaining signal integrity by providing dedicated signal paths and reducing interference between closely spaced components.
Solution Approach 2:
The patent employs a three-dimensional stacked architecture with multiple redistribution substrates arranged vertically. The first redistribution substrate is positioned between the package substrate and the interposer molding layer, while the second redistribution substrate is positioned between the interposer molding layer and the semiconductor chips. This vertical stacking in another dimension allows compact packaging while maintaining electrical performance through controlled signal paths.
2Adaptability or versatility
If multiple semiconductor chips are integrated in a compact structure, then design flexibility increases, but noise in power signals increases
Solution Approach 1:
The power delivery network is segmented into multiple dedicated paths through separate conductive patterns on the first and second redistribution substrates. Power signals are routed through distinct traces and vias, isolating noise sources and preventing interference between adjacent semiconductor chips. This segmentation allows flexible chip placement while maintaining clean power delivery to each component.
3Reliability
If redistribution substrates are used for electrical connectivity, then electrical characteristics improve, but device complexity increases
Solution Approach 1:
The interposer substrate merges multiple functions into a single integrated structure: the first redistribution substrate, second redistribution substrate, and interposer molding layer are combined to provide electrical connectivity, mechanical support, and signal routing simultaneously. This consolidation improves electrical characteristics while managing complexity by integrating multiple functions into one component rather than separate elements.
Data Source
AI summary
Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.