Interposer Package Structure for Low-Warpage Chip Bonding
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Solution Overview
Problem
The manufacturing of semiconductor packages involving interposers is complicated and costly due to the use of carrier substrates in processes like grinding and thermal compression bonding, which increase the complexity and cost.
Innovation Solution
A semiconductor package design that includes an interposer substrate with through electrodes and redistribution layers, where the through electrodes have a smaller length than the conductive posts, and uses molding members with matching thermal expansion coefficients to reduce warpage and simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If carrier substrates are used in grinding and thermal compression bonding processes, then the manufacturing process can be completed, but the process complexity and cost increase
Solution Approach 1:
The patent removes the carrier substrate from the manufacturing process entirely. The interposer substrate serves directly as the bonding substrate without requiring a separate carrier substrate, thereby simplifying the process and reducing costs while maintaining manufacturing feasibility through direct TCB bonding of chips to the interposer substrate
2Ease of manufacture
If carrier substrates are used in grinding and thermal compression bonding processes, then the manufacturing process can be completed, but manufacturing cost increases
Solution Approach 1:
The carrier substrate is extracted from the process, eliminating its associated costs. The interposer substrate directly replaces the carrier substrate's function, reducing material costs and simplifying the bill of materials while maintaining complete manufacturing capability
Solution Approach 2:
The interposer substrate serves multiple functions: it acts as both the interconnection substrate and the bonding substrate for TCB processes, eliminating the need for separate carrier substrates and reducing overall manufacturing costs while maintaining process completeness
3Ease of manufacture
If through electrodes have the same length as conductive posts, then manufacturing is simpler, but electrical characteristics and warpage control deteriorate
Solution Approach 1:
The patent applies different lengths to through electrodes versus conductive posts based on their specific functional requirements. Through electrodes are made shorter to optimize electrical characteristics and reduce warpage, while conductive posts are made longer to ensure proper mechanical and electrical connection to underlying layers, with each component's dimensions optimized for its local function
4Stability of the object's composition
If molding members with matching thermal expansion coefficients are used, then warpage is reduced, but material selection becomes more restrictive
Solution Approach 1:
The patent utilizes thermal expansion coefficient matching between the molding member and interposer substrate to minimize differential thermal expansion during processing and operation. This reduces warpage and improves package stability, though it does require careful material selection to achieve compatible thermal expansion properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the need for additional carrier substrates, lowers manufacturing costs, and enhances electrical characteristics by minimizing warpage and improving connectivity between semiconductor chips.
Implementation Method 1
molding members including a same coefficient of thermal expansion (CTE) may be formed on and beneath the interposer substrate so as to prevent or reduce warpage of the interposer substrate
Implementation Method 2
a conductive post on the second surface of the interposer substrate and contacting the through electrode
Implementation Method 3
a redistribution layer (RDL) on the first surface of the interposer substrate and on an upper surface of the through electrode and including a redistribution wiring structure
Data Source
AI summary
A semiconductor package may include an interposer substrate having first and second surfaces, a through electrode extending through the interposer substrate, an RDL on the first surface of the interposer substrate and an upper surface of the through electrode and including a redistribution wiring structure, first and second semiconductor chips electrically connected to the redistribution wiring structure on the RDL, a first molding member on the RDL and covering sidewalls of the first and second semiconductor chips, a conductive post on the second surface of the interposer substrate and contacting the through electrode, and a second molding member on the second surface of the interposer substrate and covering a sidewall of the conductive post. A maximum width of the through electrode is equal to or greater than that of the conductive post. A length of the through electrode is equal to or less than that of the conductive post.