Interposer Semiconductor Package for Taller Passive Elements
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high-speed, high-capacity, and miniaturization while maintaining reliable electrical connections and durability, particularly due to the limited space for passive elements and increased electrical path lengths.
Innovation Solution
A semiconductor package design that includes a substrate with a semiconductor chip, a passive element taller than the chip, and an interposer substrate connected by conductive structures with solder connections, allowing for a larger gap between substrates to accommodate passive elements and reduce electrical path lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a conventional semiconductor package design is used with limited space between substrate and interposer, then the package structure is compact, but the electrical path length is increased and passive element placement is restricted
Solution Approach 1:
The patent increases the vertical distance (gap) between the substrate and interposer substrate, utilizing the third dimension to accommodate taller passive elements and reduce electrical path lengths. This dimensional change allows passive elements to be positioned optimally for electrical performance while maintaining a compact overall package footprint.
Solution Approach 2:
The patent nests multiple components including passive elements, conductive structures, and interposer substrate within the vertical space above the substrate. By stacking these elements vertically rather than horizontally, the design accommodates longer electrical paths and taller passive elements without increasing the package's planar footprint.
2Adaptability or versatility
If the gap between substrate and interposer is increased to accommodate passive elements, then passive element placement flexibility is improved, but the overall package height is increased
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension to accommodate both the increased gap for passive element flexibility and the overall package height. The conductive structures extend vertically to connect the substrate to the interposer substrate, enabling passive elements to be placed at optimal positions for electrical performance while the package height increases only to the extent necessary to accommodate these vertical connections.
3Reliability
If taller passive elements are used to improve electrical characteristics, then power integrity is improved, but the space available for other components is reduced
Solution Approach 1:
The patent allows taller passive elements to be positioned in the vertical space between the substrate and interposer substrate without reducing the planar area available for other components. By utilizing the vertical dimension rather than horizontal space, the design achieves improved power integrity through taller passive elements while maintaining flexibility in component placement on the substrate surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances electrical characteristics by reducing electrical path lengths and improving power integrity and reliability, enabling miniaturization and efficient signal transmission.
Implementation Method 1
a lower solder connection portion between the substrate and the conductive structure and an upper solder connection portion between the conductive structure and the interposer substrate
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Provided is a semiconductor package. The semiconductor package may include a substrate, a semiconductor chip on the substrate, a passive element on the substrate, a conductive structure on the substrate, and an interposer substrate on the semiconductor chip, the passive element, and the conductive structure. The interposer substrate may be electrically connected to the conductive structure. A height of the passive element may be greater than a height of the semiconductor chip.