Interposer Semiconductor Package for Multi-Chip Power Integrity
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved electrical characteristics, compact size, and reduced manufacturing costs, particularly in integrating multiple semiconductor chips and capacitors effectively.
Innovation Solution
The semiconductor package incorporates a package substrate with an interposer substrate that includes a first and second redistribution substrate, an interposer molding layer, and a connection semiconductor chip, along with a capacitor chip mounted on the bottom surface of the first redistribution substrate, enhancing electrical connectivity and design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated in a conventional package structure, then functionality is enhanced, but electrical characteristics deteriorate due to increased parasitic inductance and resistance
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the package substrate and semiconductor chips. The interposer includes redistribution substrates with conductive patterns that provide optimized electrical pathways, reducing parasitic inductance and resistance while enabling multi-chip integration. The interposer acts as a mediator that improves electrical characteristics without compromising the ability to integrate multiple chips.
2Ease of manufacture
If the package structure is simplified to reduce manufacturing cost, then ease of manufacture improves, but electrical characteristics and power integrity worsen
Solution Approach 1:
The package structure is segmented into distinct functional layers: a package substrate, an interposer substrate with redistribution substrates, and mounting substrates. This segmentation allows each layer to be optimized independently - the interposer can be designed for electrical performance while the package substrate focuses on mechanical support and cost-effective manufacturing. The modular structure enables separate fabrication and assembly processes that balance manufacturing simplicity with electrical performance.
3Volume of moving object
If semiconductor chips are mounted closer together to reduce package size, then compactness improves, but manufacturing precision requirements worsen
Solution Approach 1:
The interposer substrate introduces an additional dimensional layer for electrical connectivity, allowing chips to be mounted on different planes (package substrate and mounting substrates). This vertical stacking approach reduces the horizontal footprint and package size while the interposer's conductive patterns provide precise alignment references that relax the precision requirements for chip placement. Electrical connections are established through the interposer's redistribution layers rather than requiring extremely precise direct chip-to-chip alignment.
Data Source
AI summary
Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.