Interposer Package Layout With Recessed Dielectric for Stronger Die Bonding
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Solution Overview
Problem
The semiconductor industry faces challenges in bonding integrated circuit chips directly onto substrates due to increased integration density, which has surpassed the ability to manage interposer bonding effectively, leading to limitations in three-dimensional packaging.
Innovation Solution
The solution involves bonding a logic die and a memory device to an interposer, where the exposed dielectric layer is recessed to increase the bonding area for the memory device, enhancing bonding strength and providing a larger process window for underfill filling, thereby increasing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased to improve productivity, then more components can be integrated into a given area, but the ability to bond integrated circuit chips directly onto substrates is exceeded
Solution Approach 1:
The patent transitions from two-dimensional planar packaging to three-dimensional stacked packaging by vertically stacking multiple integrated circuit chips and interposers. This dimensional change allows continued increase in integration density without exceeding substrate bonding capabilities, as the additional components are added in the vertical dimension rather than competing for horizontal substrate area.
Solution Approach 2:
The patent introduces interposers as intermediary structures between the substrate and integrated circuit chips. These interposers serve as mediator layers that redistribute electrical connections and provide mechanical support, enabling reliable bonding of high-density integrated circuits without directly bonding them to the substrate, thus resolving the bonding capability limitation.
2Strength
If the dielectric layer is recessed to increase bonding area, then bonding strength is improved, but the structural complexity increases
Solution Approach 1:
The dielectric layer is recessed in advance during the fabrication process before the integrated circuit chips are bonded to the interposer. This preliminary action creates the bonding area enhancement upfront, allowing subsequent bonding operations to proceed with improved strength without requiring complex real-time adjustments or additional bonding steps.
Solution Approach 2:
The recessing is applied locally to specific regions of the dielectric layer where bonding pads are located, rather than uniformly across the entire dielectric layer. This localized modification provides the necessary bonding area enhancement while minimizing the overall structural complexity and material removal.
Data Source
AI summary
A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.