Interposer-Overlapped Semiconductor Package for Thin Reliable Interconnects
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Solution Overview
Problem
In semiconductor packaging, it is challenging to efficiently arrange multiple semiconductor chips with high-density interconnects while minimizing package thickness and maximizing memory capacity, especially in portable electronic devices where space is limited.
Innovation Solution
A semiconductor package design incorporating a base package substrate with a redistribution layer, vertical conductive vias, and interposers that overlap semiconductor chips, allowing for efficient interconnection and signal transmission between chips, thereby reducing the need for extensive through-electrode connections and optimizing chip placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafer level packages are applied to efficiently arrange semiconductor chips in a limited structure, then the package thickness is reduced and memory capacity is increased, but the reliability of interconnection between chips deteriorates
Solution Approach 1:
An interposer is introduced as an intermediary component between semiconductor chips to establish electrical connections. The interposer includes through electrodes that penetrate its thickness and connect to redistribution layers, providing a reliable interconnection medium that enables thin packaging while maintaining connection reliability through a dedicated intermediary structure rather than direct chip-to-chip bonding.
Solution Approach 2:
The patent transitions from planar chip arrangement to a three-dimensional stacked configuration where chips are positioned above and below the interposer in the vertical dimension. This dimensional change allows efficient use of limited package volume while maintaining reliable electrical connections through the vertical through electrodes of the interposer, resolving the contradiction between thin profile and connection reliability.
2Reliability
If the number of through electrodes is increased to improve interconnection reliability, then connection reliability is enhanced, but manufacturing complexity and costs increase
Solution Approach 1:
The interconnection function is segmented between the interposer's through electrodes and the redistribution layers formed on its surfaces. This segmentation allows the through electrodes to provide vertical connectivity while the redistribution layers handle lateral signal routing, simplifying the overall manufacturing process by dividing the complex interconnection task into manageable functional segments rather than requiring all connections to be made through electrodes alone.
Solution Approach 2:
The patent implements different interconnection densities in different regions: through electrodes provide high-density vertical connections where needed in the interposer, while redistribution layers provide flexible lateral connections at the chip interfaces. This local quality approach optimizes manufacturing complexity by using the appropriate connection method in each spatial region rather than uniformly increasing through electrode count throughout the entire structure.
Data Source
AI summary
A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.