Interposer Package Stacking With Through-Insulator Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density integration and efficient interconnects due to limitations in reducing feature size and packaging size, which hinders the development of advanced three-dimensional integration technologies for wafer-level packaging.
Innovation Solution
A manufacturing method involving the formation of an interposer with multiple metal layers and an insulating structure, where a core substrate is layered with conductive and insulating materials, and through holes are filled with insulating material, enabling electrical connections and encapsulation of semiconductor dies, followed by a redistribution layer for efficient packaging and stacking of packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then more electronic components can be integrated into a given area, but manufacturing precision requirements increase and production costs rise
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration through wafer-level packaging and stacked package structures. Multiple semiconductor wafers are bonded together in vertical layers, achieving high integration density without further reducing lateral feature sizes. This dimensional shift allows continued scaling while maintaining manufacturable feature dimensions.
Solution Approach 2:
The patent implements nested packaging structures where smaller packages are integrated within larger package assemblies. Multiple semiconductor dies and interposer structures are nested within encapsulant materials, creating compact hierarchical arrangements that maximize component density while simplifying individual component manufacturing requirements.
2Area of stationary object
If package size is reduced to accommodate smaller components, then area utilization improves, but packaging complexity and manufacturing difficulty increase
Solution Approach 1:
The patent moves packaging from a single-plane layout to multi-layer vertical stacking. Packages are arranged in stacked configurations along the vertical axis, dramatically reducing the footprint area while distributing complexity across multiple manageable layers rather than compressing everything into a single crowded plane.
Solution Approach 2:
The patent divides the packaging system into discrete modular layers including semiconductor wafers, interposer structures, encapsulant materials, and redistribution layers. Each layer can be manufactured and prepared independently, then bonded together, which simplifies the manufacturing process compared to creating a single complex integrated structure.
3Quantity of substance
If three-dimensional integration technology is implemented to achieve high-density packaging, then integration capacity increases, but manufacturing process complexity and production costs increase
Solution Approach 1:
The patent performs preliminary preparation of semiconductor wafers, interposer structures, and encapsulant materials before final assembly. Redistribution layers are pre-formed on interposers, and bonding interfaces are prepared in advance, allowing the actual stacking and bonding process to proceed more efficiently with reduced on-site complexity.
Solution Approach 2:
The patent introduces interposer structures as intermediary components between semiconductor dies and external connections. These interposers provide redistribution layers and mechanical support, simplifying the bonding process and enabling flexible routing of electrical connections without requiring direct complex interconnections between all components.
4Reliability
If heterogeneous integration is pursued for high-performance interconnects, then system performance improves, but manufacturing adaptability and process flexibility requirements increase
Solution Approach 1:
The patent creates a universal packaging platform using standard wafer-level processes and common encapsulant materials that can accommodate different types of semiconductor devices. The interposer structures provide universal bonding interfaces and redistribution capabilities that work with various die types, enabling heterogeneous integration without requiring entirely separate manufacturing lines for each device combination.
Data Source
AI summary
A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.