Interposer Substrate Package Layout for Warpage-Reliable Connections
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving reliable interconnection between the interposer substrate and the package substrate, particularly due to warpage issues during manufacturing.
Innovation Solution
The semiconductor package design includes a package substrate with specific wiring pads and connection parts, along with an interposer substrate mounted on these connections, featuring substrate connection parts and chip connection pillars for reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an interposer substrate is mounted on a package substrate to enable high functionalization and miniaturization, then the functionality and integration density are improved, but warpage issues occur during manufacturing that compromise interconnection reliability
Solution Approach 1:
The package structure is segmented into distinct functional layers: package substrate, interposer substrate, and semiconductor chips. The interposer substrate acts as an independent intermediate layer with its own wiring layers and connection structures, allowing each layer to be optimized separately while maintaining overall reliability despite warpage
Solution Approach 2:
The interposer substrate serves as an intermediary component between the package substrate and semiconductor chips. It includes substrate connection parts that connect to the package substrate and chip connection pillars that connect to the chips, mediating the mechanical and electrical connections while accommodating dimensional mismatches and warpage through its independent structure
2Volume of moving object
If multiple semiconductor chips are stacked on the interposer substrate to achieve miniaturization, then the package size is reduced, but stress and warpage during manufacturing increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Multiple semiconductor chips are arranged in vertical layers on the interposer substrate, achieving miniaturization by utilizing the vertical dimension while the interposer substrate's wiring layers provide stress management pathways
Solution Approach 2:
The interposer substrate features locally optimized structures including specific wiring layers (first, second, third wiring layers) and connection structures (substrate connection parts, chip connection pillars) positioned at different locations to manage stress distribution and accommodate warpage in different regions of the stacked package
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances interconnection reliability between the interposer and package substrates, effectively addressing warpage-related stress and ensuring stable electrical connections for semiconductor chips.
Implementation Method 1
a first wiring connection part formed on the first wiring pad and including a wiring solder layer
Data Source
AI summary
Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.