Wafer-Level Interposer Packaging for 3D IC Density
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Solution Overview
Problem
Current semiconductor technologies face limitations in increasing circuit density due to physical constraints in two-dimensional integration, leading to increased interconnections and power consumption, and existing 3D IC formation techniques struggle to minimize form factor and reduce stress between dies and substrates.
Innovation Solution
The use of wafer-level packaging with an interposer and double-sided die bonding, where through-substrate vias and conductive joints provide electrical connections between dies and a packaging substrate, reducing stress and eliminating the need for TSVs in dies, thus minimizing size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional integration is used to increase circuit density, then more components can be integrated into a given chip area, but the minimum feature size limit and increased interconnection complexity restrict further density improvements
Solution Approach 1:
The patent transitions from two-dimensional integration to three-dimensional integration by stacking multiple dies vertically. This dimensional change allows continued increase in circuit density without proportionally increasing interconnection complexity, as vertical stacking provides direct access between layers through through-substrate vias rather than requiring extensive lateral interconnections.
2Productivity
If traditional 3D IC bonding techniques are used to stack dies, then circuit density increases, but stress between dies and substrate increases and form factor cannot be minimized
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary between the stacked dies and the packaging substrate. This interposer absorbs and distributes mechanical stress, preventing stress concentration at the die-substrate interfaces. The interposer acts as a buffer layer that accommodates thermal expansion differences and mechanical mismatches between components.
3Reliability
If through-substrate vias are formed in dies for electrical connections, then electrical coupling between dies is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the through-substrate via formation process from the die manufacturing and relocates it to the interposer substrate. By forming vias only in the interposer rather than in each die, the manufacturing process is simplified while maintaining reliable electrical connections between stacked dies. This extraction reduces the number of high-precision via formation steps required.
4Volume of moving object
If package-on-package or interposer techniques are used for stacking dies, then form factor is reduced, but x-y dimension cannot be minimized due to 2.5D limitations
Solution Approach 1:
The patent implements full three-dimensional stacking with dies positioned at different vertical levels, utilizing the z-dimension more effectively than 2.5D techniques. By forming vias through the interposer and enabling direct vertical connections, the design achieves true 3D integration that minimizes the x-y footprint while maximizing vertical utilization, overcoming the limitations of planar or partially-planar approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances circuit density, reduces stress and power consumption, and minimizes the size and cost of semiconductor devices by eliminating the need for TSVs in dies and using a packaging substrate, while maintaining die quality.
Implementation Method 1
at least two dies or wafers are bonded together and electrical connections are formed between each die and contact pads on a substrate
Implementation Method 2
through-substrate vias and conductive joints provide electrical connections between dies and a packaging substrate
Data Source
AI summary
A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.