Multi-Piece Interposer Packaging for Semiconductor Warpage Control

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Solution Overview

Problem

Semiconductor packages face warpage issues due to differing thermal expansion coefficients of materials, leading to stress concentration and reduced productivity and reliability.

Innovation Solution

A semiconductor package design featuring an interposer with multiple pieces and a molding member with a higher thermal expansion coefficient than the interposer, which alleviates warpage by alternating components with different expansion coefficients on the same plane.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If materials with different thermal expansion coefficients are used in the semiconductor package, then the package can accommodate thermal stress, but warpage occurs due to differential expansion

Engineering Contradiction:
Improvethermal stress accommodationVSAvoidwarpage
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The patent applies thermal expansion principle by selecting a molding member with a thermal expansion coefficient higher than that of the interposer. This deliberate mismatch in thermal expansion coefficients allows the molding member to compensate for the differential expansion between the interposer and other package components, thereby reducing warpage while accommodating thermal stress.

Inventive Principle:
Principle #37Thermal expansion

Solution Approach 2:

The patent uses composite materials by combining the interposer (with lower thermal expansion coefficient) and the molding member (with higher thermal expansion coefficient) in a layered structure. This composite construction allows the different materials to work together, with the molding member's higher expansion coefficient compensating for stress concentration and reducing overall package warpage.

Inventive Principle:
Principle #40Composite materials

2Productivity

If an interposer is used to arrange semiconductor chips efficiently, then integration density increases, but stress concentration occurs due to material mismatches

Engineering Contradiction:
Improveintegration densityVSAvoidstress concentration
Core Design Contradiction:
ProductivityVSStress or pressure

Solution Approach 1:

The molding member acts as an intermediary between the interposer and the external environment. By having a higher thermal expansion coefficient than the interposer, the molding member absorbs and distributes thermal stress, preventing stress concentration at the interposer and protecting the integrated chip structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Shape

If the molding member has a higher thermal expansion coefficient than the interposer, then warpage is reduced, but material selection becomes more constrained

Engineering Contradiction:
Improvewarpage reductionVSAvoidmaterial selection flexibility
Core Design Contradiction:
ShapeVSAdaptability or versatility

Solution Approach 1:

The patent changes the key parameter of thermal expansion coefficient by selecting a molding member with a higher coefficient than the interposer. This parameter change enables warpage reduction while the patent provides guidance on suitable material combinations, maintaining practical versatility in material selection.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design minimizes stress concentration and enhances the productivity and reliability of the semiconductor package by effectively managing thermal expansion-related warpage.

Implementation Method 1

a thermal expansion coefficient of the molding member is greater than a thermal expansion coefficient of the interposer

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS11837581B2Semiconductor package
Publication Date: 2023.12.05 SAMSUNG ELECTRONICS CO LTD
  • US11837581B2 patent drawing
  • US11837581B2 patent drawing
  • US11837581B2 patent drawing

AI summary

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.