Interposer Pad Recess Structure for High-Bandwidth Packaging

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving high memory bandwidth due to limitations in data transmission speed and number of connection bumps, necessitating an innovative interposer design to enhance connectivity and integration.

Innovation Solution

An interposer with a base layer, wiring structure, protective layers, and through electrodes, featuring pad recesses and protruding pads, along with alignment keys, to increase the number and density of connection points, thereby enhancing data transmission capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of connection bumps is increased to enhance memory bandwidth, then data transmission capability is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvememory bandwidthVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces pad recesses that extend vertically into the interposer protective layer, creating a multi-level pad structure. This vertical dimensionality allows connection pads to be positioned at different heights, increasing the effective connection density without proportionally increasing the footprint area, thereby enhancing memory bandwidth while managing device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interposer is segmented into multiple functional layers including base layer, protective layer, and pad recess structures. This segmentation allows independent optimization of each layer - the base layer provides structural support, the protective layer offers mechanical protection, and the pad recesses create specialized connection zones, enabling high connection density without overwhelming manufacturing complexity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the density of connection pads is increased to improve data transmission, then memory bandwidth is enhanced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedata transmission speedVSAvoidmanufacturing precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Pad recesses are formed in the interposer protective layer before final pad assembly. This preliminary action creates pre-defined, precisely positioned recesses that guide pad placement and alignment, reducing the actual manufacturing precision required during the final assembly stage while still achieving high connection density.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pad recess structure acts as an intermediary between the base layer and the connection pads. It provides a mechanically stable, pre-formed interface that facilitates precise pad positioning without requiring extreme precision in the pad attachment process itself, thereby enabling high data transmission speeds with manageable manufacturing precision requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If more wiring layers are added to increase connectivity, then number of data transmission lines increases, but device complexity and warpage increase

Engineering Contradiction:
Improvenumber of data transmission linesVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent utilizes vertical pad recesses to create multi-level connection points, allowing data transmission lines to be routed through different vertical levels. This enables increased connectivity without adding proportional horizontal wiring layers, as connections can be established at multiple heights within the same footprint area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The pad recess structures are nested within the interposer protective layer, with connection pads positioned within these recesses. This nested arrangement allows multiple connection levels to be integrated within a compact vertical space, increasing the number of data transmission lines without proportionally increasing overall device complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

4Productivity

If the interposer structure is optimized for high connection density, then memory bandwidth increases, but structural stability and warpage control become challenging

Engineering Contradiction:
Improvememory bandwidthVSAvoidstructural stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The interposer protective layer is selectively removed to form pad recesses only at specific locations where connections are needed. This local modification approach maintains the overall structural integrity and stability of the protective layer while creating localized connection zones that enable high connection density for enhanced memory bandwidth.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The pad recesses are pre-formed in the protective layer before final assembly, creating a stable, pre-configured structure. This preliminary action ensures that the protective layer maintains its structural stability throughout the manufacturing process, while the pre-defined recesses facilitate high-density connections for improved memory bandwidth.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12417988B2Interposer, method for fabricating the same, and semiconductor package having the same
Publication Date: 2025.09.16 SAMSUNG ELECTRONICS CO LTD
  • US12417988B2 patent drawing
  • US12417988B2 patent drawing
  • US12417988B2 patent drawing

AI summary

An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.