Interposer Pad-Free Layout for Void-Free Semiconductor Molding

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Solution Overview

Problem

The existing 2.5D semiconductor package manufacturing process faces challenges with void formation due to the reduced fluidity of molding material between the interposer and semiconductor devices, leading to incomplete filling and reduced package reliability.

Innovation Solution

Incorporating a pad-free region with a cross-shaped structure on the interposer, which serves as an injection passage for the molding material, ensuring complete filling of gaps between the interposer and semiconductor devices without the need for separate underfill processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wafer-level molding process is used, then manufacturing efficiency is improved, but molding material fluidity is reduced causing voids

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidpackage reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The interposer surface is segmented into pad-free regions and pad regions, where pad-free regions serve as injection passages for molding material. This segmentation allows the molding material to flow through designated pathways, ensuring complete filling while maintaining manufacturing efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pad-free region acts as an intermediary structure that facilitates the flow of molding material between the mold cavity and the bonding pads. By providing this intermediate pathway, the molding material can reach all necessary areas without being blocked by bonding pads, thus preventing void formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If bonding pads are placed in all mounting regions, then electrical connectivity is improved, but molding material flow is blocked causing incomplete filling

Engineering Contradiction:
Improveelectrical connectivityVSAvoidfilling completeness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The mounting region is divided into pad-free regions and pad regions. Bonding pads are exclusively placed in pad regions, while pad-free regions remain clear to allow molding material flow. This spatial segmentation resolves the conflict between electrical connectivity and material flow.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the interposer are assigned different functions: pad-free regions provide fluid passage for molding material, while pad regions provide electrical connectivity. This local differentiation allows each region to optimize its specific function without compromising the other.

Inventive Principle:
Principle #3Local quality

3Reliability

If separate underfill process is added, then void prevention is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvevoid preventionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The functions of molding and underfilling are merged into a single molding process. The pad-free regions enable the molding material to simultaneously perform both encapsulation and gap-filling functions, eliminating the need for a separate underfill process and reducing manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The molding material serves multiple functions: it provides mechanical protection, electrical insulation, and void prevention. By designing the pad-free regions, the same molding process achieves what would traditionally require separate underfilling, demonstrating multi-functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250006698A1Semiconductor package and method of manufacturing semiconductor package
Publication Date: 2025.01.02 SAMSUNG ELECTRONICS CO LTD
  • US20250006698A1 patent drawing
  • US20250006698A1 patent drawing
  • US20250006698A1 patent drawing

AI summary

A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions.