3D Interposer Passive Layout for Heat and EMI Control
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing size and increasing efficiency due to the exponential increase in I/O pins and thermal energy management, which affects the performance of processors and memory components, and there is a need for a more efficient use of space and reduced electromagnetic interference.
Innovation Solution
The implementation of a Chip on Wafer on Substrate (CoWoS) architecture with vertically arranged passive and active devices, where magnetic core inductors are placed between the interposer and the substrate, and deep trench capacitors are positioned on opposing sides of the interposer, utilizing through-silicon vias for thermal management and electromagnetic interference reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If devices are reduced in size to meet consumer demand, then device dimensions decrease, but thermal energy management becomes more difficult and electromagnetic interference increases
Solution Approach 1:
The patent transitions from planar 2D arrangement of components to a three-dimensional vertical stacking architecture. Multiple device layers are stacked vertically with interconnect structures connecting different layers, enabling compact form factor while providing dedicated thermal management pathways and electromagnetic shielding between layers.
Solution Approach 2:
The device is divided into multiple functional layers stacked vertically, with each layer containing specific components. Thermal management is segmented into dedicated thermal vias and heat dissipation structures separate from the active device layers, allowing independent optimization of thermal pathways.
2Area of stationary object
If devices are reduced in size through vertical stacking, then space efficiency improves, but manufacturing complexity increases
Solution Approach 1:
Interconnect structures such as through-silicon vias and conductive pillars are formed in advance during the semiconductor fabrication process before final device assembly. This preliminary formation of vertical interconnects simplifies subsequent stacking operations and reduces overall manufacturing complexity despite the three-dimensional architecture.
3Adaptability or versatility
If I/O pins are increased exponentially to support more functions, then device functionality improves, but electromagnetic interference and thermal management become more difficult
Solution Approach 1:
The patent moves I/O connections from a two-dimensional planar array to a three-dimensional vertical architecture. Multiple I/O connections are distributed across different vertical layers, with electromagnetic shielding and ground structures positioned between layers to reduce interference while maintaining high I/O capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances thermal dissipation, reduces electromagnetic interference, and optimizes space usage, leading to improved performance and reliability of semiconductor devices while maintaining economical fabrication.
Implementation Method 1
utilizing through-silicon vias for thermal management
Implementation Method 2
magnetic core inductors are placed between the interposer and the substrate
Implementation Method 3
deep trench capacitors are positioned on opposing sides of the interposer
Data Source
AI summary
A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.