Interposer Pitch Conversion for Compact 3D IC Packaging
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Solution Overview
Problem
Existing three-dimensional integrated circuit devices face an issue of increased size due to the uniform pitch between signal TSVs and signal bumps, leading to unused regions and larger device dimensions.
Innovation Solution
Implementing a first pitch for signal TSVs in the first semiconductor chip that is narrower than the second pitch for signal bumps in the second semiconductor chip, with an interposer connecting them, thereby reducing the occupying area of the signal TSVs and allowing for a smaller integrated circuit device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pitch between signal TSVs is made the same as the pitch between signal bumps, then electrical connection reliability is improved, but the occupying area of signal TSVs increases and device size increases
Solution Approach 1:
The patent applies asymmetry by setting different pitch values for signal TSVs and signal bumps. Specifically, the pitch between adjacent signal TSVs is configured to be different from the pitch between adjacent signal bumps, creating an asymmetric layout that reduces the occupying area of signal TSVs while maintaining reliable electrical connections through the interposer
Solution Approach 2:
The patent applies local quality by optimizing the pitch configuration locally in the first semiconductor chip. The signal TSVs are arranged with a specific pitch that is adapted to the local requirements of the TSV structure, while the signal bumps have a different pitch suited to their local configuration, allowing each component to occupy minimal space while maintaining functionality
2Ease of manufacture
If the pitch between signal TSVs is increased to match signal bump pitch, then manufacturing alignment is simplified, but the overall device size increases due to unused regions
Solution Approach 1:
The patent applies parameter changes by varying the pitch parameter for signal TSVs independently from the pitch parameter for signal bumps. This allows optimization of the TSV pitch to minimize device area while the interposer compensates for the parameter difference to maintain manufacturing feasibility and alignment
3Object-generated harmful factors
If signal TSVs are arranged with wider spacing, then signal interference is reduced, but the occupying area increases and device size increases
Solution Approach 1:
The patent uses asymmetric pitch configuration where the signal TSV pitch is optimized independently from signal bump pitch, allowing sufficient spacing to reduce signal interference between TSVs while minimizing the overall occupying area through optimized layout arrangement
Data Source
AI summary
An integrated circuit device including a first semiconductor chip, a plurality of signal through silicon vias (TSV), a second semiconductor chip, a plurality of signal bumps and an interposer may be provided. The signal TSVs may be in the first semiconductor chip by a first pitch. The second semiconductor chip may be on the first semiconductor chip. The signal bumps may be on a lower surface of the second semiconductor chip by a second pitch wider than the first pitch. The interposer may be interposed between the first semiconductor chip and the second semiconductor chip and may be electrically connecting the signal TSVs with the signal bumps. Thus, an occupying area of the signal TSVs in the first semiconductor chip may be decreased so that the integrated circuit device may have a smaller size.