Interposer Planarization for Low-TTV Chiplet Package Assembly
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving precise control over manufacturing tolerances for chiplet formation due to the downsizing of device dies, which requires tight control over total thickness variation (TTV) to prevent failures in through-silicon vias and ensure reliable packaging.
Innovation Solution
A front side planarization technique is employed to achieve a total thickness variation of less than 3 μm by flipping and thinning the interposer to expose through-silicon vias, allowing for precise mounting of device dies and forming a chiplet die stack with reduced TTV, enabling the integration of multiple semiconductor substrates with advanced technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dies are downsized to increase integration density, then component density is improved, but manufacturing precision deteriorates due to tighter control requirements over total thickness variation
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming through-silicon vias with initial thickness, depositing first connectors, performing planarization to reduce TTV, then forming second connectors and bonding device dies. This segmentation allows each stage to be optimized independently, particularly the planarization step that specifically addresses TTV control.
Solution Approach 2:
The planarization process is performed as a preliminary action before bonding the device dies to the interposer. By reducing TTV in advance through planarization, the subsequent bonding process can proceed with tighter tolerances, enabling reliable connection of downsized device dies without requiring extreme precision throughout the entire manufacturing chain.
2Reliability
If through-silicon vias are formed in thick substrates, then connectivity is improved, but manufacturing precision deteriorates due to increased total thickness variation
Solution Approach 1:
The planarization process replaces mechanical thickness variations with a controlled chemical-mechanical polishing or etching process. This substitution allows precise control over the final substrate thickness and TTV, enabling through-silicon vias to be formed with consistent dimensions even in thick substrates, thereby maintaining both connectivity and manufacturing precision.
3Manufacturing precision
If planarization is performed to reduce TTV, then manufacturing precision is improved, but device complexity increases due to additional process steps
Solution Approach 1:
The planarization step is merged with the existing connector formation process. The same dielectric material deposition and patterning tools used for forming first and second connectors are also used for planarization, combining multiple functions into a single integrated process module. This reduces the overall device complexity despite adding the TTV control function.
4Reliability
If multiple connectors are formed over through-silicon vias, then reliability is improved, but device complexity increases due to additional structure layers
Solution Approach 1:
The first and second connectors are designed with universal functionality, serving both as electrical interconnects and as mechanical support structures. The same connector geometry and material composition are used for both layers, allowing them to perform multiple functions simultaneously: providing electrical pathways, reducing stress concentration, and maintaining structural integrity. This universality reduces device complexity by eliminating the need for differentiated connector designs.
Data Source
AI summary
A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.