Interposer Planarization for Low-TTV Semiconductor Packages
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Solution Overview
Problem
The challenge in semiconductor manufacturing is achieving precise control over manufacturing tolerances and reducing total thickness variation (TTV) in die stacks as device dies shrink, particularly in forming chiplets with through-silicon vias, to prevent failures and enhance integration density.
Innovation Solution
A front side planarization technique is employed, followed by flipping and thinning the interposer to expose through-silicon vias, ensuring a total thickness variation of less than 3 μm, which involves forming bond pads, solder regions, and planarizing dielectric layers to achieve precise alignment and connection of device dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dies are shrunk to increase integration density, then more components can be integrated into a given area, but manufacturing tolerances and total thickness variation become harder to control
Solution Approach 1:
The patent performs planarization of the interposer before mounting the device dies. This preliminary action creates a flat surface that compensates for subsequent thickness variations, ensuring that even as device dies shrink and integration density increases, the total thickness variation remains controlled within acceptable limits (e.g., less than 3 μm).
Solution Approach 2:
The patent changes the physical state and dimensions of the interposer by thinning it to a controlled thickness (e.g., 50-150 μm) and planarizing its surface. These parameter changes enable precise control over total thickness variation while maintaining high integration density through the use of multiple stacked dies.
2Quantity of substance
If through-silicon vias are formed in smaller device dies, then integration density increases, but alignment precision and connection reliability become more difficult to ensure
Solution Approach 1:
The patent performs planarization of the interposer surface before mounting device dies and forming connections. This preliminary flattening action ensures that through-silicon vias can be accurately aligned with bond pads even as device die sizes shrink, maintaining connection reliability through precise positioning and reduced misalignment risks.
3Quantity of substance
If multiple device dies are stacked to increase integration density, then functional integration is enhanced, but total thickness variation increases making manufacturing more difficult
Solution Approach 1:
The patent planarizes the interposer surface before stacking multiple device dies. This preliminary flattening action compensates for thickness variations that would otherwise accumulate with each additional die in the stack, enabling high integration density while keeping total thickness variation within controllable limits and simplifying subsequent manufacturing steps.
Solution Approach 2:
The interposer serves as an intermediary substrate that provides a planar mounting surface for multiple device dies. By thinning and planarizing this intermediary layer, the patent enables precise positioning and stacking of multiple dies, managing the complexity of high-density integration through a controlled intermediate structure.
Data Source
AI summary
A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.