Interposer Power Module Assembly for Low-Inductance Die Mounting
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Solution Overview
Problem
Conventional power electronics assemblies face challenges in processing unpackaged semiconductor dies, such as IGBTs or MOSFETs, in standard surface-mount device (SMD) production lines due to the need for clean-room conditions and high inductance attachment.
Innovation Solution
The design of loadable power modules with a power substrate, switchable dies, and an interposer that allows electrical contacting through contact elements, enabling low-inductance attachment and encapsulation in insulation material, facilitating processing in conventional production lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If unpackaged semiconductor dies are processed in standard SMD production lines, then manufacturing cost and complexity are reduced, but clean-room conditions and low inductance attachment cannot be ensured
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the semiconductor die and the printed circuit board. This interposer includes a recess that receives and encapsulates the unpackaged semiconductor die, providing both mechanical support and electrical connection while maintaining low inductance. The interposer allows standard SMD processing to be used while ensuring clean-room conditions are maintained during die attachment.
2Device complexity
If conventional power modules are used, then assembly is simplified, but inductance is high and power density is limited
Solution Approach 1:
The patent segments the power module into modular components: a printed circuit board with multiple recesses, multiple interposers, and multiple semiconductor dies. Each recess can independently receive and encapsulate a die, allowing for flexible configuration. This segmentation enables low-inductance design by minimizing current path lengths while maintaining assembly simplicity through standardized modular components.
Solution Approach 2:
The patent utilizes the vertical dimension by creating recesses that extend downward from the surface of the printed circuit board. This allows the semiconductor dies to be positioned below the board surface, reducing the inductance of current loops while maintaining a compact form factor. The interposers bridge the vertical gap between the die and the board surface, enabling three-dimensional packaging that improves power density.
3Reliability
If more insulation material is used to surround the die, then electrical isolation is improved, but thermal conductivity and power density decrease
Solution Approach 1:
The patent applies insulation material locally only in the recess areas where semiconductor dies are mounted, rather than using extensive insulation throughout the module. The recesses are filled with insulation material that provides electrical isolation for each individual die while minimizing the total volume of insulating material. This localized approach maintains electrical isolation reliability while preserving thermal pathways and reducing thermal resistance.
Data Source
AI summary
Various embodiments of the teachings herein include a power electronics assembly having a substrate with two loadable power modules. The two modules each comprise: a power substrate with a first metallization; a switchable die with power interfaces; an interposer; and two contact elements, each of which provides an electrical contact for one of the power interfaces at the interposer. The die is joined to the metallization of the power substrate and to the interposer. A gap is defined between the first substrate, the interposer, and the die, and closed off by an insulation material so the die is surrounded by the insulation material, the power substrate, and the interposer. At least one of the contact elements projects through the interposer and/or is part of the interposer.