Active Silicon Interposer Power Sequencing for Multi-Rail ASICs
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Solution Overview
Problem
In large datacenter server systems, managing power sequencing across multiple power rails is complex and space-intensive, requiring multiple sequencers that complicate board-level design and management.
Innovation Solution
Implementing logic and delay circuitry in a silicon interposer, controlled by an ASIC or on-board controller, to function as an in-package power sequencer for power rails, allowing for integrated power sequencing within the interposer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple dedicated sequencers are used to manage power sequencing across multiple power rails, then power sequencing control is achieved, but board space increases and design complexity increases
Solution Approach 1:
The patent combines multiple sequencer functions into a single integrated sequencer device that can control multiple power rails through a master-slave configuration. The master sequencer coordinates with slave sequencers to manage power sequencing across numerous rails, reducing the total number of independent sequencer components needed on the board while maintaining comprehensive control capability.
Solution Approach 2:
The sequencer is designed with universal control capabilities to manage multiple power rails through programmable firmware. A single sequencer can adapt to control different numbers and configurations of power rails by loading appropriate sequencing profiles, eliminating the need for dedicated hardware for each rail and reducing overall system complexity.
2Ease of operation
If multiple dedicated sequencers are used to manage power sequencing, then comprehensive power rail control is achieved, but board space consumption increases
Solution Approach 1:
The patent consolidates multiple sequencer functions into a single integrated device that controls multiple power rails through master-slave coordination. This merging approach significantly reduces the total board space required compared to using multiple independent sequencers, as the shared control logic and firmware repository are centralized in one location rather than replicated across multiple components.
3Ease of operation
If a master-slave configuration of multiple sequencers is used, then control of large number of power rails is achieved, but board level design management becomes harder
Solution Approach 1:
The master-slave sequencer configuration incorporates feedback mechanisms where slave sequencers report status and receive coordination signals from the master. This structured feedback loop simplifies design management by providing clear hierarchical control relationships and standardized communication protocols, making the system easier to manage than ad-hoc multi-sequencer arrangements.
Data Source
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AI summary
An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.