Semiconductor Package Interposer Recesses Memory Stacking
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in miniaturization due to increased signal latency and power loop inductance caused by stacked DRAM configurations, which result in signal integrity impairments and higher z-height, making it difficult to achieve both performance scaling and device miniaturization.
Innovation Solution
The use of a semiconductor package with a silicon interposer featuring a redistribution layer and through silicon vias, where stacked memory devices are positioned within recesses in the interposer rather than on the top surface, creating a 'opposum' configuration that reduces interconnect length and improves channel impedance matching, thereby enhancing signal and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If stacked DRAM configurations are used to achieve miniaturization, then device form-factor is reduced, but signal latency increases and signal integrity deteriorates
Solution Approach 1:
The patent transitions from planar 2D packaging to three-dimensional stacked packaging, placing memory devices vertically above the SOC die. This dimensional change enables miniaturization by utilizing the z-axis space, reducing the footprint area while accommodating multiple memory stacks to achieve higher bandwidth density
Solution Approach 2:
The patent embeds multiple memory devices within a compact stacked hierarchy, nesting several DRAM devices vertically. Each memory stack is positioned in a recess of the interposer, creating a nested configuration where memory devices are integrated into the vertical structure of the package, achieving high density within a small form-factor
2Productivity
If stacked DRAM configurations are used to increase bandwidth density, then device miniaturization is achieved, but z-height increases
Solution Approach 1:
The patent divides the memory package into multiple discrete stacks, each containing one or more memory devices positioned in separate recesses of the interposer. This segmentation allows independent optimization of each stack's height and position, enabling bandwidth density scaling while managing overall z-height through selective placement and recess depth control
Solution Approach 2:
The patent creates local variations in the package structure by forming recesses at specific locations in the interposer with varying depths and dimensions. Each recess is tailored to accommodate specific memory device stacks, allowing local optimization of z-height in different areas of the package while maintaining high bandwidth density through strategic placement
3Length of moving object
If adjacent transmission lines are placed close together in stacked configurations, then interconnect length is reduced, but electrical coupling noise increases
Solution Approach 1:
The patent introduces an interposer as an intermediary substrate between the SOC die and memory devices. The interposer contains redistribution layers and through-silicon vias that route signals, providing physical separation and impedance control between adjacent transmission lines. This intermediary structure reduces electrical coupling noise while maintaining compact interconnect lengths through optimized signal routing paths
4Loss of time
If DRAM packages are placed on the top side of SOC package, then signal latency is reduced, but package real-estate is occupied
Solution Approach 1:
The patent utilizes the vertical z-dimension by placing memory devices in recesses of the interposer rather than only on the top surface. This three-dimensional arrangement allows signal latency reduction through direct vertical interconnects while minimizing package real-estate occupation by efficiently utilizing vertical space and recess depth instead of horizontal area
Data Source
AI summary
The present disclosure is directed to semiconductor packages, and methods for making them, which includes a package substrate, an interposer with a redistribution layer positioned on the interposer. A recess may be formed in a bottom surface in the interposer and a plurality of through silicon vias may be formed in the interposer, including the recess, that are coupled to a bottom surface of the redistribution layer. A recess device may be positioned in the recess and coupled to the redistribution layer. A top-side device may be positioned on and coupled to a top surface of the redistribution layer, and a footprint of the top-side device may be aligned to overlap the recess device. In an aspect, the recess device and the top-side device may be stacked memory devices, e.g., DRAMs, SRAMs, and/or other memory devices.