Interposer Recess and Underfill Structure for Dense Bump Packaging
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high memory bandwidth due to limitations in the number and density of connection bumps, which restricts their performance and speed, especially in compact and multifunctional electronic products.
Innovation Solution
The semiconductor package design incorporates a silicon interposer with recesses on its bottom surface, a stack structure of semiconductor chips, and a dual underfill layer system, where the first underfill layer surrounds the interposer connection terminals and partially covers the recesses, while the second underfill layer surrounds the side surface of the first underfill layer, enhancing the connection density and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number and density of connection bumps are increased to achieve high memory bandwidth, then the memory bandwidth is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent introduces recesses in the bottom surface of the interposer, creating a three-dimensional structure that allows connection bumps to be arranged in multiple levels. This vertical dimension enables increased connection density without proportionally increasing the horizontal footprint, thereby improving memory bandwidth while controlling device complexity
Solution Approach 2:
The recesses in the interposer create nested structures where connection bumps can be positioned within the recessed areas, effectively nesting the connection architecture. This allows for higher density connections by utilizing the vertical space within the interposer structure rather than only horizontal expansion
2Quantity of substance
If the number and density of connection bumps are increased to achieve high memory bandwidth, then the memory bandwidth is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The recesses are pre-formed in the interposer bottom surface before the connection bumps are attached. This preliminary structuring provides predetermined positioning features that guide the placement of connection bumps, reducing the precision requirements during the bump attachment process and simplifying manufacturing
3Quantity of substance
If the connection density is increased to improve memory bandwidth, then the memory bandwidth is improved, but the reliability and stability of connections may deteriorate
Solution Approach 1:
The recesses create localized regions with different structural properties compared to the flat interposer surface. The recessed areas provide enhanced mechanical interlocking and stress distribution for connection bumps, improving local connection reliability and stability while allowing higher overall connection density
Data Source
AI summary
A semiconductor package includes: a base substrate; an interposer disposed on the base substrate, wherein the interposer includes a plurality of recesses in a bottom surface thereof; a semiconductor chip disposed on the interposer; a plurality of interposer connection terminals between the interposer and the base substrate, wherein the plurality of interposer connection terminals electrically connect the interposer to the base substrate; and a first underfill layer disposed between the interposer and the base substrate, wherein the first underfill layer at least partially surrounds the plurality of interposer connection terminals, wherein the first underfill layer at least partially surrounds a side surface of each of the plurality of recesses and has a slope declining from the bottom surface of the interposer to a top surface of the base substrate.