Semiconductor Package Interposer Reduces Landing Pad Width

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Solution Overview

Problem

Conventional semiconductor packages require large landing pads and redistribution layers due to placement errors, leading to congested routing and larger chip sizes, which is undesirable for smaller, less congested packages.

Innovation Solution

A semiconductor package design that includes a base with a redistribution layer, die placement, and an interposer with reduced landing pad size, allowing for increased placement accuracy and closer line/spacing in interconnections, eliminating the need for an internal redistribution layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If large landing pads are used to accommodate placement errors, then die alignment reliability is improved, but package area and routing congestion increase

Engineering Contradiction:
Improvedie alignment reliabilityVSAvoidpackage area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

An interposer is introduced as an intermediary component between the dies and the package substrate. The interposer contains an embedded redistribution layer (RDL) that mediates the interconnection function, allowing smaller landing pads on the dies while maintaining reliable alignment through the interposer's larger, more tolerant connection interfaces.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The redistribution layer is moved from the package substrate plane to a separate interposer component that sits in a different dimensional layer. This separates the RDL function from the substrate, allowing independent optimization of landing pad size on dies versus RDL trace spacing on the interposer, thus reducing the conflict between alignment tolerance and routing density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If large landing pads are used for die alignment, then placement error tolerance is improved, but line/spacing of interconnection routings increases

Engineering Contradiction:
Improveplacement error toleranceVSAvoidinterconnection routing density
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The interposer with embedded RDL acts as a mediator that decouples the relationship between die landing pad size and interconnection routing density. The RDL on the interposer can have optimized trace spacing independent of the die landing pad dimensions, allowing dense routing while maintaining tolerance for placement errors through the interposer's alignment features.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The interconnection function is segmented into two separate components: the die landing pads and the interposer's embedded RDL. This segmentation allows each component to be optimized independently - landing pads can be sized for alignment tolerance while the RDL traces can be spaced for dense routing, eliminating the direct coupling that caused the original contradiction.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If embedded RDL interconnections are used in the substrate, then die interconnection is achieved, but routing congestion and chip size increase

Engineering Contradiction:
Improvedie interconnection capabilityVSAvoidchip size
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The interposer serves as an intermediary that carries the embedded RDL function outside the main package substrate. This allows the substrate to be smaller since it doesn't need to accommodate the RDL, while the interposer provides the interconnection capability with optimized routing density and reduced congestion.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The RDL is relocated from the substrate plane to a separate interposer component in a different dimensional layer. This separates the RDL routing function from the substrate area, allowing the substrate to be minimized while the interposer handles the interconnection routing with optimized spacing and reduced congestion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9355963B2Semiconductor package interconnections and method of making the same
Publication Date: 2016.05.31 QUALCOMM INC
  • US9355963B2 patent drawing
  • US9355963B2 patent drawing
  • US9355963B2 patent drawing

AI summary

A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.