Processor Interposer Retimer for PCIe CXL Protocol Conversion
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Solution Overview
Problem
Current computing systems face limitations in flexibility and efficiency for data communication between processors and expansion devices due to limited bus configurations, leading to delays and compatibility issues with different PCIe devices.
Innovation Solution
A CPU/GPU interposer with a retimer/redriver circuit that facilitates communication between processors and expansion devices by modulating signals between different high-speed protocols, such as PCIe and CXL, allowing for various bus bifurcation configurations and reducing the need for costly processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a processor supports only one type of bus configuration, then the processor design is simplified, but the system flexibility and compatibility with different PCIe devices are reduced
Solution Approach 1:
An interposer is introduced as an intermediary component between the processor and PCIe devices. The interposer contains a protocol conversion circuit that translates between different bus protocols (PCIe and CXL), allowing the processor to communicate with various PCIe devices without requiring multiple processor types. This resolves the contradiction by maintaining simple processor design while achieving system flexibility through the intermediary interposer.
2Adaptability or versatility
If a processor directly communicates with multiple different types of PCIe devices, then compatibility is improved, but the processor cost and complexity increase
Solution Approach 1:
The interposer serves as a mediator that handles protocol conversion between the processor and diverse PCIe devices. By placing the protocol conversion circuit in the interposer rather than the processor, the system achieves broad device compatibility while keeping the processor design simple and cost-effective.
Solution Approach 2:
The interposer is designed as a separate, replaceable component that can be optimized for specific protocol conversion needs without increasing processor cost. This allows the expensive processor to remain simple while the interposer handles the complexity of supporting multiple device types.
3Length of stationary object
If signal transmission distance between processor and PCIe devices is increased, then system scalability is improved, but signal integrity and communication reliability deteriorate
Solution Approach 1:
The interposer acts as an intermediary signal transmission component that includes retimer/redriver circuits. These circuits refresh and retransmit signals, allowing extended transmission distances between the processor and PCIe devices while maintaining signal integrity. The interposer effectively resets signal timing and amplitude, enabling scalable system designs without compromising communication reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The interposer enables flexible and efficient high-speed data communication, supporting multiple PCIe devices with reduced power consumption and cost, while allowing for different bus configurations, thus enhancing system performance and compatibility.
Implementation Method 1
A CPU/GPU interposer with a retimer/redriver circuit that facilitates communication between processors and expansion devices by modulating signals between different high-speed protocols, such as PCIe and CXL
Data Source
AI summary
A system and method for providing efficient communication between a processor and a device. An interposer is provided to send signals from the processor to the device. The interposer includes a printed circuit board, a first interconnection port communicating with the processor, and a second interconnection port communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port, and the retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.