Interposer Routing for Semiconductor Package Assembly
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Solution Overview
Problem
The shrinking dimensions of semiconductor features in integrated circuit devices pose challenges for conventional routing configurations of power and/or ground signals in electronic package assemblies.
Innovation Solution
The use of a substrate with an interposer, which is configured to electrically couple the semiconductor die to the opposite side of the substrate, allowing for efficient routing of power and/or ground signals through the interposer, either using printed circuit board materials or semiconductor materials, and employing techniques such as flip-chip configurations and wirebonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional routing configurations are used for power and ground signals, then the routing is simple and straightforward, but the routing becomes ineffective and unreliable as semiconductor feature dimensions shrink
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the substrate and the semiconductor die. This interposer contains through-silicon vias (TSVs) that serve as conductive pathways, mediating the electrical connection between power/ground pads on the substrate and corresponding pads on the semiconductor die. The interposer thus enables reliable signal routing without requiring complex routing configurations within the substrate or die itself.
Solution Approach 2:
The patent transitions from planar routing configurations to three-dimensional vertical routing by implementing through-silicon vias (TSVs) that extend vertically through the interposer. This dimensional change allows power and ground signals to be routed in the vertical direction rather than requiring complex lateral routing paths, thereby achieving reliable signal transmission while maintaining routing simplicity.
2Productivity
If semiconductor feature dimensions are reduced to enable scaling, then device capacity and integration increase, but conventional routing configurations become inadequate for power and ground signal transmission
Solution Approach 1:
The patent enables continued device scaling by implementing vertical through-silicon via routing in the interposer, which decouples the routing function from the scaling constraints of conventional planar configurations. This allows semiconductor features to continue shrinking for increased integration while power and ground signals are transmitted reliably through the vertical TSV pathways that are insensitive to lateral dimension reductions.
Solution Approach 2:
The interposer acts as a mediator that isolates the scaling challenges of semiconductor die from the routing requirements. As the die shrinks to increase integration capacity, the interposer with its fixed TSV routing structure maintains reliable power and ground signal transmission, effectively decoupling the scaling process from routing reliability concerns.
3Reliability
If an interposer with through-silicon vias is used to route power and ground signals, then signal routing reliability improves, but the device structure and manufacturing process become more complex
Solution Approach 1:
The patent segments the electrical coupling function into distinct components: the substrate provides mechanical support and I/O connections, the interposer provides vertical TSV routing for power and ground, and the semiconductor die provides active circuitry. This segmentation allows each component to be optimized independently, with the interposer specifically designed to provide reliable electrical coupling through its TSV structure, while the overall package assembly remains modular and manageable.
Data Source
AI summary
Embodiments of the present disclosure provide an apparatus comprising a substrate having (i) a first side configured to receive a semiconductor die and (ii) a second side disposed opposite to the first side. The substrate comprises a printed circuit board material. The apparatus further comprises an interposer that is (i) disposed in the substrate and (ii) configured to electrically couple the first side of the substrate and the second side of the substrate. The interposer comprises a semiconductor material.